US5668038A
Expired / Lapsed
US
⏱️ 0.0 years remaining
One step smooth cylinder surface formation process in stacked cylindrical DRAM products
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 1996-10-09
•
Granted: 1997-09-16
•
Expires: 2016-10-09
Abstract
Abstract A method of fabrication of a DRAM cell, which forms an improved smooth top cylinder surface and provides controllable cylinder height. A semiconductor structure is provided having a transistor. Also provided are a barrier layer 12 over a first insulating layer 11 on the semiconductor structure. A polysilicon plug 14 extends through the barrier layer 12 and the insulating layer 11. A second insulating layer 16 is formed over portions of the barrier layer 12 and has an opening over the polysilicon plug 14 and over portions of the barrier layer adjacent to the polysilicon plug 14. A polysilicon layer 18 is formed over the second insulating layer 16, the sidewalls of the second insulating layer 16, the portions of the barrier layer 12 adjacent to the polysilicon plug 14 and over the polysilicon plug 14. A gap filling third insulating layer 20 is formed over the polysilicon layer 18. In an important process, potions of the gap filling third insulating layer 20 and the polysilicon layer 18 are etched back in an one step etch process to form a polysilicon cylinder 22. The critical one step etch processes is comprised of two stages: (1) an insulating layer etch stage and (2) a polysilicon etch stage. The second insulating layer 16 and the third insulating layer 20 are then removed thereby formed a stacked polysilicon cylinder.
Inventors
- 👤 Yuan-Chang Huang
- 👤 Chen-Jong Wang
- 👤 Mong-Song Liang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 14:09
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
221 words
A method of forming a polysilicon cylinder having a smooth top surface comprising; a) providing a barrier layer over a first insulating layer on a semiconductor substrate, a polysilicon plug extending through said barrier layer and said insulating layer, a second insulating layer over portions of said barrier layer, said second insulating layer having an opening over said polysilicon plug and over portions of said barrier layer adjacent to said polysilicon plug, said opening defined by sidewalls of said second insulating layer, a polysilicon layer over said second insulating layer, over said sidewalls of said second insulating layer, over said portions of said barrier layer adjacent to said polysilicon plug and over said polysilicon plug, a gap filling third insulating layer over said polysilicon layer; b) etching back portions of said gap filling third insulating layer and said polysilicon layer in a one step etch process to form a polysilicon cylinder; said one step etch process comprised of two stages: (1) an insulating layer etch stage and (2) a polysilicon etch stage, said insulating layer etch stage comprising a plasma enhanced etch using CHF 3 , CF 4 , and Argon gasses, and said polysilicon etch stage using CF 4 , SF 6 , and Argon gasses; and c) removing said second insulating layer and said gap filling third insulating layer.
Claim 2
Independent Claim
221 words
A method of forming a polysilicon cylinder having a smooth top surface comprising; a) providing a barrier layer over a first insulating layer on a semiconductor substrate, a polysilicon plug extending through said barrier layer and said insulating layer, a second insulating layer over portions of said barrier layer, said second insulating layer having an opening over said polysilicon plug and over portions of said barrier layer adjacent to said polysilicon plug, said opening defined by sidewalls of said second insulating layer, a polysilicon layer over said second insulating layer, over said sidewalls of said second insulating layer, over said portions of said barrier layer adjacent to said polysilicon plug and over said polysilicon plug, a gap filling third insulating layer over said polysilicon layer; b) etching back portions of said gap filling third insulating layer and said polysilicon layer in a one step etch process to form a polysilicon cylinder; said one step etch process comprised of two stages: (1) an insulating layer etch stage and (2) a polysilicon etch stage, said insulating layer etch stage comprising a plasma enhanced etch using CHF 3 , CF 4 , and Argon gasses, and said polysilicon etch stage using CF 4 , SF 6 , and Argon gasses; and c) removing said second insulating layer and said gap filling third insulating layer.
Claim 3
Dependent Claim
155 words
The method of claim 1 wherein said insulating layer etch stage comprises: a CHF 3 flow rate of between about 30 and 40 sccm, a CF 4 flow rate of between about 40 and 50 sccm, and an Argon flow rate of between about 500 and 900 sccm and at a pressure of between about 700 and 900 mTorr and a power of between about 1200 and 1400 watts and for a duration of between about 60 and 100 sec; and said polysilicon etch stage comprises: a SF 6 flow rate of between about 15 and 50 sccm, an CF 4 flow rate of between about 55 and 80 sccm, and an Argon flow rate of between about 500 and 800 sccm and at a pressure of between about 1000 and 1500 mTorr and at a power of between about 500 and 1000 watts and for a duration of between about 10 and 20 sec.
Claim 4
Dependent Claim
30 words
The method of claim 1 wherein said second insulting layer is PETEOS and said one step etch process comprises an etch ratio between PETEOS:polysilicon is between about 0.9:1.1 and 1.1:0.9.
Claim 5
Dependent Claim
22 words
The method of claim 1 wherein said barrier layer has a thickness in the range of between about 500 and 1500 Å.
Claim 6
Dependent Claim
23 words
The method of claim 1 wherein said second insulating layer has a thickness in a range of between about 4000 and 6000 Å.
Claim 7
Dependent Claim
19 words
The method of claim 1 wherein said polysilicon layer has a thickness of between about 800 and 1200 Å.
Claim 8
Dependent Claim
17 words
The method of claim 1 wherein said gap filling third insulating layer is composed of silicon oxide.
Claim 9
Dependent Claim
29 words
The method of claim 1 wherein the removal of said second insulating layer and said gap filling third insulating layer comprises a wet etch using a buffered oxide etch.
Claim 10
Dependent Claim
19 words
The method of claim 1 wherein said substrate further includes a source and said polysilicon plug contacts said source.
Claim 11
Dependent Claim
19 words
The method of claim 1 wherein said polysilicon cylinder has a height of between about 4000 and 6000 Å.
Claim 12
Independent Claim
256 words
A method of forming a polysilicon cylinder having a smooth top surface in a DRAM cell comprising; a) providing a barrier layer over a first insulating layer on a substrate, said barrier layer composed of silicon nitride, said first insulating layer composed of silicon oxide, a polysilicon plug extending through a plug opening in said barrier layer and said first insulating layer contacting said substrate; b) forming a second insulating layer composed of silicon oxide over said barrier layer and said polysilicon plug; c) etching said second insulating layer forming a cylindrical opening over said polysilicon plug and exposing portions of said barrier layer; said cylindrical opening defined by sidewalls of said second insulating layer; d) depositing a polysilicon layer over said second insulating layer, over said sidewalls of said second insulating layer, over said polysilicon plug, and over exposed portions of said barrier layer; e) depositing a gap filling third insulating layer composed of silicon oxide over said polysilicon layer (18); f) etching back portions of said gap filling third insulating layer and said polysilicon layer in a one step etch process to form a polysilicon cylinder, said one step etch process comprising two stages: (1) an insulating layer etch stage and (2) a polysilicon etch stage, said insulating layer etch stage comprising a plasma enhanced etch using CHF 3 , CF 4 , and Argon gasses, said polysilicon etch stage using CF 4 , SF 6 , and Argon gasses; and g) removing said second insulating layer and said gap filling third insulating layer.
Claim 13
Independent Claim
256 words
A method of forming a polysilicon cylinder having a smooth top surface in a DRAM cell comprising; a) providing a barrier layer over a first insulating layer on a substrate, said barrier layer composed of silicon nitride, said first insulating layer composed of silicon oxide, a polysilicon plug extending through a plug opening in said barrier layer and said first insulating layer contacting said substrate; b) forming a second insulating layer composed of silicon oxide over said barrier layer and said polysilicon plug; c) etching said second insulating layer forming a cylindrical opening over said polysilicon plug and exposing portions of said barrier layer; said cylindrical opening defined by sidewalls of said second insulating layer; d) depositing a polysilicon layer over said second insulating layer, over said sidewalls of said second insulating layer, over said polysilicon plug, and over exposed portions of said barrier layer; e) depositing a gap filling third insulating layer composed of silicon oxide over said polysilicon layer (18); f) etching back portions of said gap filling third insulating layer and said polysilicon layer in a one step etch process to form a polysilicon cylinder, said one step etch process comprising two stages: (1) an insulating layer etch stage and (2) a polysilicon etch stage, said insulating layer etch stage comprising a plasma enhanced etch using CHF 3 , CF 4 , and Argon gasses, said polysilicon etch stage using CF 4 , SF 6 , and Argon gasses; and g) removing said second insulating layer and said gap filling third insulating layer.
Claim 14
Dependent Claim
22 words
The method of claim 11 wherein said barrier layer has a thickness in the range of between about 500 and 1500 Å.
Claim 15
Dependent Claim
76 words
The method of claim 11 wherein said second insulating layer is deposited by a plasma enhanced tetraethylorthosilicate (PETEOS) process at a pressure of between about 7 and 8 Torr, at a temperature of between about 400° and 450° C., at a power of between about 500 and 600 W, and using gasses comprising of tetraethylorthosilicate (TEOS) and Helium, and said second insulating layer has a thickness in a range of between about 4000 and 6000 Å.
Claim 16
Dependent Claim
103 words
The method of claim 11 wherein the etching of said second insulating layer is performed by anisotropic reactive ion etching with Argon (Ar)+carbon tetrafluoride (CF 4 )+Nitrogen (N 2 ) at a pressure of between about 275 and 330 mTorr, at a power of between about 1250 and 1350 watts, using CF 4 at a flow rate of between about 75 and 85 sccm, using Ar at a flow rate of between about 550 and 650 sccm, and using N 2 at a flow rate of between about 90 and 110 sccm and an electrode spacing of between about 0.9 and 1.1 cm.
Claim 17
Dependent Claim
28 words
The method of claim 11 wherein said polysilicon layer is deposited by low pressure chemical vapor deposition (LPCVD) to a thickness of between about 800 and 1200 Å.
Claim 18
Dependent Claim
60 words
The method of claim 11 wherein said gap filling third insulating layer is deposited by a plasma enhanced tetraethylorthosilicate (PETEOS) process at a pressure of between about 7 and 8 Torr, at a temperature of between about 400° and 450° C., at a power of between about 500 and 600 watts, and using gasses comprising of tetraethylorthosilicate (TEOS) and Helium.
Claim 19
Dependent Claim
155 words
The method of claim 11 wherein said insulating layer etch stage comprises: a CHF 3 flow rate of between about 30 and 40 sccm, a CF 4 flow rate of between about 40 and 50 sccm, and an Argon flow rate of between about 500 and 900 sccm and at a pressure of between about 700 and 900 mTorr and a power of between about 1200 and 1400 watts and for a duration of between about 60 and 100 sec, and said polysilicon etch stage comprises: a SF 6 flow rate of between about 15 and 50 sccm, a CF 4 flow rate of between about 55 and 80 sccm, and an Argon flow rate of between about 500 and 800 sccm and at a pressure of between about 1000 and 1500 mTorr and at a power of between about 500 and 1000 watts and for a duration of between about 10 and 20 sec.
Claim 20
Dependent Claim
23 words
The method of claim 13 wherein said one step etch process comprises an etch ratio between PETEOS:polysilicon is between about 0.9:1.1 and 1.1:0.9.
Claim 21
Dependent Claim
30 words
The method of claim 11 wherein the removal of said second insulating layer and said gap filling third insulating layer comprising of a wet etch using a buffered oxide etch.
Claim 22
Dependent Claim
19 words
The method of claim 11 wherein said substrate further includes a source and said polysilicon plug contacts said source.
Claim 23
Dependent Claim
19 words
The method of claim 11 wherein said polysilicon cylinder has a height of between about 4000 and 6000 Å.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-15 | 2001-03-17 | 2001-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-15 | 2005-03-17 | 2005-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-15 | 2009-03-17 | 2009-09-16 | $7700.00 | Window Closed / Lapsed |