US5539231A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic random access memory device having reduced stepped portions
Assignee: Renesas Electronics Corp
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Filing: 1995-03-02
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Granted: 1996-07-23
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Expires: 2015-03-02
Abstract
Abstract A first conductive layer and a second conductive layer are formed apart from each other on a surface of a semiconductor substrate. A first contact hole for exposing a surface of first conductive layer is formed in an interlayer insulating film. A first interconnection layer is buried in first contact hole so as to be in contact with first conductive layer. The position of the surface of first interconnection layer is the same as or lower than the surface of interlayer insulating film. The surface of first interconnection layer is covered with an insulating film. A second contact hole for exposing a surface of second conductive layer is provided in interlayer insulating film. A second conductive layer is connected to second conductive layer through second contact hole.
Inventors
- 👤 Toshifumi Suganaga
- 👤 Eiichi Ishikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:31
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10D; H10D1/00; H10D1/60; H10D1/68; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10W20/071; H10W20/081; H10W20/092; H10W20/40; H10W20/41; H10W20/44; H10W20/4451
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
168 words
A semiconductor device, comprising: a semiconductor substrate; a first conductive layer and a second conductive layer formed apart from each other on a surface of said semiconductor substrate, an interlayer insulating film having an upper surface and formed on said semiconductor substrate, a first contact hole for exposing a surface of said first conductive layer being formed in said interlayer insulating film; a first interconnection layer having an upper surface and filling said first contact hole so as to be in contact with said first conductive layer, the upper surface of said first interconnection layer extending to a height no greater than the upper surface of said interlayer insulating film; an insulating film covering the upper surface of said first interconnection layer; a second contact hole formed in said interlayer insulating film for exposing a surface of said second conductive layer; and a second interconnection layer provided on said interlayer insulating film so as to be in contact with said second conductive layer through said second contact hole.
Claim 2
Dependent Claim
168 words
A semiconductor device, comprising: a semiconductor substrate; a first conductive layer and a second conductive layer formed apart from each other on a surface of said semiconductor substrate, an interlayer insulating film having an upper surface and formed on said semiconductor substrate, a first contact hole for exposing a surface of said first conductive layer being formed in said interlayer insulating film; a first interconnection layer having an upper surface and filling said first contact hole so as to be in contact with said first conductive layer, the upper surface of said first interconnection layer extending to a height no greater than the upper surface of said interlayer insulating film; an insulating film covering the upper surface of said first interconnection layer; a second contact hole formed in said interlayer insulating film for exposing a surface of said second conductive layer; and a second interconnection layer provided on said interlayer insulating film so as to be in contact with said second conductive layer through said second contact hole.
Claim 3
Dependent Claim
20 words
A semiconductor device as recited in claim 1, wherein the thickness of said insulating film is at least 0.05 μm.
Claim 4
Dependent Claim
16 words
A semiconductor device as recited in claim 1, wherein said semiconductor device includes a bipolar transistor.
Claim 5
Dependent Claim
211 words
A semiconductor device, comprising: a semiconductor substrate; a gate electrode formed on said semiconductor substrate; a pair of source/drain layers provided in a surface of said semiconductor substrate on both sides of said gate electrode; an interlayer insulating film having an upper surface and provided on said semiconductor substrate, covering said gate electrode, a first contact hole for exposing a surface of one of said source/drain layers being provided in said interlayer insulating film; a buried bit interconnection layer having an upper surface and buried in said first contact hole so as to be electrically connected to said one source/drain layer, the upper surface of said buried bit interconnection layer extending to a height no greater than the upper surface of said interlayer insulating film; an insulating film covering the upper surface of said buried bit interconnection layer; a second contact hole provided in said interlayer insulating film for exposing a surface of the other of said source/drain layers; a storage node interconnection provided on said interlayer insulating film so as to be connected to said the other source/drain layer through said second contact hole; a dielectric film covering a surface of said storage node interconnection; and a cell place electrode covering said storage node interconnection with said dielectric film therebetween.
Claim 6
Dependent Claim
211 words
A semiconductor device, comprising: a semiconductor substrate; a gate electrode formed on said semiconductor substrate; a pair of source/drain layers provided in a surface of said semiconductor substrate on both sides of said gate electrode; an interlayer insulating film having an upper surface and provided on said semiconductor substrate, covering said gate electrode, a first contact hole for exposing a surface of one of said source/drain layers being provided in said interlayer insulating film; a buried bit interconnection layer having an upper surface and buried in said first contact hole so as to be electrically connected to said one source/drain layer, the upper surface of said buried bit interconnection layer extending to a height no greater than the upper surface of said interlayer insulating film; an insulating film covering the upper surface of said buried bit interconnection layer; a second contact hole provided in said interlayer insulating film for exposing a surface of the other of said source/drain layers; a storage node interconnection provided on said interlayer insulating film so as to be connected to said the other source/drain layer through said second contact hole; a dielectric film covering a surface of said storage node interconnection; and a cell place electrode covering said storage node interconnection with said dielectric film therebetween.
References Cited (Backward Citations)
US5012309A
Cited
EP0488283A2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-23 | 2000-01-22 | 2000-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-23 | 2004-01-22 | 2004-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-23 | 2008-01-22 | 2008-07-23 | $7700.00 | Window Closed / Lapsed |