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US5668037A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of forming a resistor and integrated circuitry having a resistor construction

Assignee: Micron Technology Inc
•
Filing: 1996-07-11
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Granted: 1997-09-16
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Expires: 2016-07-11
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Abstract

Abstract A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars. An integrated circuit incorporating a resistor construction includes, i) a layer of semiconductive material; ii) a pair of electrically conductive pillars provided within the semiconductive material layer, the pair of pillars being separated from one another and thereby having a mass of the semiconductive material extending therebetween; and iii) an electrically conductive node in electrical connection with each of the respective conductive pillars. Alternately, a resistor is provided within a semiconductive substrate using different concentration diffusion regions.

Inventors

  • 👤 Kirk Prall
  • 👤 Pierre C. Fazan
  • 👤 Aftab Ahmad
  • 👤 Howard E. Rhodes
  • 👤 Werner Juengling
  • 👤 Pai-Hung Pan
  • 👤 Tyler Lowrey

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-10 02:16
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10D84/00; H10D84/201; H10D84/204; H10D84/209; H10D84/80; H10D84/811; H10D84/817; Y; Y10; Y10S; Y10S148/00; Y10S148/136

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 247 words
A method of forming a resistor within a semiconductive substrate from semiconductive material comprising the following steps: doping a first region of the semiconductive substrate with a conductivity enhancing impurity of a first type and to a first electrically resistive dopant concentration; forming a spaced pair of second diffusion regions of conductivity enhancing impurity of the first type within the semiconductive substrate to a second electrically conductive dopant concentration, the spaced second diffusion regions contacting the first region and having first region semiconductive material extending therebetween; forming a transistor gate in a second region of the semiconductive substrate, the gate being encapsulated by an insulative material; after forming the second diffusion regions and transistor gate, forming an insulating layer outwardly of the semiconductive substrate and over both the first region and the transistor gate; forming a pair of first openings into the insulating layer to the semiconductive substrate, the respective first openings overlying the pair of second diffusion regions, the forming of the pair of first openings also comprising in the same step etching a pair of second openings through the insulating layer to the semiconductive substrate immediately adjacent the transistor gate in a manner substantially selective relative to the encapsulating insulative material, the etching exposing the substrate while etching the insulating layer selectively relative to the encapsulating insulative material, wherein a portion of said insulating layer covers all of the transistor gate after said etch; and forming electrically conductive material within the pair of first openings.
Claim 2
Independent Claim 247 words
A method of forming a resistor within a semiconductive substrate from semiconductive material comprising the following steps: doping a first region of the semiconductive substrate with a conductivity enhancing impurity of a first type and to a first electrically resistive dopant concentration; forming a spaced pair of second diffusion regions of conductivity enhancing impurity of the first type within the semiconductive substrate to a second electrically conductive dopant concentration, the spaced second diffusion regions contacting the first region and having first region semiconductive material extending therebetween; forming a transistor gate in a second region of the semiconductive substrate, the gate being encapsulated by an insulative material; after forming the second diffusion regions and transistor gate, forming an insulating layer outwardly of the semiconductive substrate and over both the first region and the transistor gate; forming a pair of first openings into the insulating layer to the semiconductive substrate, the respective first openings overlying the pair of second diffusion regions, the forming of the pair of first openings also comprising in the same step etching a pair of second openings through the insulating layer to the semiconductive substrate immediately adjacent the transistor gate in a manner substantially selective relative to the encapsulating insulative material, the etching exposing the substrate while etching the insulating layer selectively relative to the encapsulating insulative material, wherein a portion of said insulating layer covers all of the transistor gate after said etch; and forming electrically conductive material within the pair of first openings.
Claim 3
Dependent Claim 39 words
The method of forming a resistor of claim 1, wherein the forming of the electrically conductive material within the pair of first openings also comprises in the same step, forming electrically conductive material within the pair of second openings.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-09-15 2001-03-17 2001-09-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-09-15 2005-03-17 2005-09-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-09-15 2009-03-17 2009-09-16 $7700.00 Window Closed / Lapsed

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