US5666545A
Expired / Lapsed
US
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Direct access video bus computer system and method for transferring video information using a dedicated video bus
Assignee: Intel Corp
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Filing: 1994-05-11
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Granted: 1997-09-09
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Expires: 2014-05-11
Abstract
Abstract In a computer system, a direct access, independently arbitrated video bus (connected to a personal computer (PC) -compatible video subsystem) is directly coupled to one or more dual-ported processors to eliminate video cycle traffic over the system bus or buses and I/O bus, thereby improving system performance. The preferred embodiment architecture has, in addition to the video bus, multiple processors coupled to at least two independently arbitrated system buses which are coupled to at least two independently arbitrated input/output (I/O) buses, to provide for rapid bus information signal transfer rates.
Inventors
- 👤 Jay A. Marshall
- 👤 Thomas F. Heil
- 👤 Donald H. Parsons, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 09:53
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/14
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
162 words
A computer system, comprising: a system bus; a video bus which handles video cycle information; a video subsystem coupled to said video bus; a processor having a first port and a second port, said processor coupled via the first port to said video bus and via the second port to said system bus; means for causing said processor to perform a first video cycle via the first port over said video bus so as to cause data to be transferred between said processor and said video subsystem over said video bus in accordance with the first video cycle while concurrently performing a memory cycle via the second port over said system bus so as to cause data to be transferred over said system bus in accordance with the memory cycle; means for disabling said video bus; and means for causing said processor to perform a second video cycle via the second port over said system bus if said video bus is disabled.
Claim 2
Dependent Claim
162 words
A computer system, comprising: a system bus; a video bus which handles video cycle information; a video subsystem coupled to said video bus; a processor having a first port and a second port, said processor coupled via the first port to said video bus and via the second port to said system bus; means for causing said processor to perform a first video cycle via the first port over said video bus so as to cause data to be transferred between said processor and said video subsystem over said video bus in accordance with the first video cycle while concurrently performing a memory cycle via the second port over said system bus so as to cause data to be transferred over said system bus in accordance with the memory cycle; means for disabling said video bus; and means for causing said processor to perform a second video cycle via the second port over said system bus if said video bus is disabled.
Claim 3
Dependent Claim
197 words
A computer system, comprising: a system bus; a memory coupled to said system bus; a video bus; a video subsystem coupled to said video bus; a processor having a first port and a second port, said processor being coupled to said video bus via the first port and to said system bus via the second port; and means for causing said processor to execute a first video cycle via the first port over said video bus so as to cause data to be transferred between said processor and said video subsystem over said video bus in accordance with the first video cycle while concurrently executing a memory cycle via the second port over said system bus so as to cause data to be transferred between said processor and said memory over said system bus in accordance with the memory cycle; means for disabling said video bus; and means for causing said processor to execute a second video cycle via the second port over said system bus while, said video bus is disabled, so as to cause data to be transferred between said processor and said memory over said system bus in accordance with the second video cycle.
Claim 4
Dependent Claim
197 words
A computer system, comprising: a system bus; a memory coupled to said system bus; a video bus; a video subsystem coupled to said video bus; a processor having a first port and a second port, said processor being coupled to said video bus via the first port and to said system bus via the second port; and means for causing said processor to execute a first video cycle via the first port over said video bus so as to cause data to be transferred between said processor and said video subsystem over said video bus in accordance with the first video cycle while concurrently executing a memory cycle via the second port over said system bus so as to cause data to be transferred between said processor and said memory over said system bus in accordance with the memory cycle; means for disabling said video bus; and means for causing said processor to execute a second video cycle via the second port over said system bus while, said video bus is disabled, so as to cause data to be transferred between said processor and said memory over said system bus in accordance with the second video cycle.
Claim 5
Dependent Claim
219 words
A computer system, comprising: a system bus; a memory coupled to said system bus; a video bus; a video subsystem coupled to said video bus; a processor having a first port and a second port, said processor being coupled to said video bus via the first port and to said system bus via the second port; and means for causing said processor to execute a first video cycle via the first port over said video bus so as to cause data to be transferred between said processor and said video subsystem over said video bus in accordance with the first video cycle while concurrently executing a memory cycle via the second port over said system bus so as to cause data to be transferred between said processor and said memory over said system bus in accordance with the memory cycle; an input/output bus coupled to said system bus and to said video subsystem; means for disabling said video bus; and means for causing said processor to execute a second video cycle via the second port over said system bus and said input/output bus, while said video bus is disabled, so as to cause data to be transferred between said processor and said video subsystem over said system bus and said I/O bus in accordance with the second video cycle.
Claim 6
Dependent Claim
219 words
A computer system, comprising: a system bus; a memory coupled to said system bus; a video bus; a video subsystem coupled to said video bus; a processor having a first port and a second port, said processor being coupled to said video bus via the first port and to said system bus via the second port; and means for causing said processor to execute a first video cycle via the first port over said video bus so as to cause data to be transferred between said processor and said video subsystem over said video bus in accordance with the first video cycle while concurrently executing a memory cycle via the second port over said system bus so as to cause data to be transferred between said processor and said memory over said system bus in accordance with the memory cycle; an input/output bus coupled to said system bus and to said video subsystem; means for disabling said video bus; and means for causing said processor to execute a second video cycle via the second port over said system bus and said input/output bus, while said video bus is disabled, so as to cause data to be transferred between said processor and said video subsystem over said system bus and said I/O bus in accordance with the second video cycle.
Claim 7
Independent Claim
178 words
A method for transferring data in a computer system having a processor, a video subsystem, a memory, a video bus, and a system bus, comprising the steps of: performing a first video cycle via a first port of the processor over the video bus so as to cause data to be transferred between the processor and the video subsystem over the video bus in accordance with the first video cycle; and performing a memory cycle via a second port of the processor over the system bus so as to cause data to be transferred between the processor and the memory over the system bus in accordance with the memory cycle, wherein the memory cycle performing step is performed during the first video cycle performing step; disabling the video bus; and performing a second video cycle via the second port of the processor over the system bus, while the video bus is disabled, so as to cause data to be transferred between the processor and the video subsystem over the system bus in accordance with the second video cycle.
Claim 8
Independent Claim
178 words
A method for transferring data in a computer system having a processor, a video subsystem, a memory, a video bus, and a system bus, comprising the steps of: performing a first video cycle via a first port of the processor over the video bus so as to cause data to be transferred between the processor and the video subsystem over the video bus in accordance with the first video cycle; and performing a memory cycle via a second port of the processor over the system bus so as to cause data to be transferred between the processor and the memory over the system bus in accordance with the memory cycle, wherein the memory cycle performing step is performed during the first video cycle performing step; disabling the video bus; and performing a second video cycle via the second port of the processor over the system bus, while the video bus is disabled, so as to cause data to be transferred between the processor and the video subsystem over the system bus in accordance with the second video cycle.
Claim 9
Independent Claim
201 words
A method for transferring data in a computer system having a processor, a video subsystem, a memory, a video bus, and a system bus, comprising the steps of: performing a first video cycle via a first port of the processor over the video bus so as to cause data to be transferred between the processor and the video subsystem over the video bus in accordance with the first video cycle; and performing a memory cycle via a second port of the processor over the system bus so as to cause data to be transferred between the processor and the memory over the system bus in accordance with the memory cycle, wherein the memory cycle performing step is performed during the first video cycle performing step, wherein the computer system also has an input/output bus, and further comprising the steps of: disabling the video bus; and performing a second video cycle via the second port of the processor over the system bus and the input/output bus, while the video bus is disabled, so as to cause data to be transferred between the processor and the video subsystem over the system bus and the I/O bus in accordance with the second video cycle.
Claim 10
Independent Claim
201 words
A method for transferring data in a computer system having a processor, a video subsystem, a memory, a video bus, and a system bus, comprising the steps of: performing a first video cycle via a first port of the processor over the video bus so as to cause data to be transferred between the processor and the video subsystem over the video bus in accordance with the first video cycle; and performing a memory cycle via a second port of the processor over the system bus so as to cause data to be transferred between the processor and the memory over the system bus in accordance with the memory cycle, wherein the memory cycle performing step is performed during the first video cycle performing step, wherein the computer system also has an input/output bus, and further comprising the steps of: disabling the video bus; and performing a second video cycle via the second port of the processor over the system bus and the input/output bus, while the video bus is disabled, so as to cause data to be transferred between the processor and the video subsystem over the system bus and the I/O bus in accordance with the second video cycle.
References Cited (Backward Citations)
US4513390A
Cited
US4564915A
Cited
US4597016A
Cited
US4631598A
Cited
EP0188828A2
Cited
US4604743A
Cited
US4815033A
Cited
US4967375A
Cited
US4835712A
Cited
US4914570A
Cited
EP0263799A2
Cited
US4862154A
Cited
US4952149A
Cited
US5122973A
Cited
US5008816A
Cited
US4965559A
Cited
US5025249A
Cited
US4992961A
Cited
WO1991015910A1
Cited
US5245322A
Cited
US5254983A
Cited
US5267334A
Cited
US5269005A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-08 | 2001-03-10 | 2001-09-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-08 | 2005-03-10 | 2005-09-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-08 | 2009-03-10 | 2009-09-09 | $7700.00 | Window Closed / Lapsed |