EP0188828A2 — Image processing apparatus and intercommunication…

Claim 1

Independent Claim 268 words

An image apparatus, comprising: - a plurality of device stations for data acquisition, data processing, data storage and/or data display (28, 30, 34, 36, 38, 40, 42, 44, 48, 50) - a synchronous video bus (20) interconnecting all of said devices for communicating digital image information therebetween at vide data rates; - a low speed bus interconnecting said devices for communicating control information therebetween; characterized in that - said video bus comprising a time-multiplexed address selection bus, a timing and synchronization bus, and a plurality of N dynamically allocatable data sub-buses; - said address selection bus and each of said data sub-buses comprising a plurality of parallel data lines; - system clock means for producing a periodic signal on the clock bus which defines sequential time slots (BSYSCK); - packet clock means for producing a periodic signal on the clock bus which defines sequential packet slots, each of said packet slots comprising at least N time slots and being synchronized therewith (BPACKETCK); - each of said devices comprising means for transmitting and/or receiving a packet of N serial words of data on each of one or more allocated sub-buses during a packet slot and in synchronization with said time slots; - each of said devices further comprises means for transmitting and/or receiving a single word of address information during a single allocated time slot in each packet which time slot is uniquely allocated (VADDVAL) with the data sub-bus allocated to the device; - whereby said sub-buses are spatially multiplexed among said processes and said address bus is time-multiplexed among a plurality of processes executable in respective device stations.

Claim 2

Dependent Claim 268 words

An image apparatus, comprising: - a plurality of device stations for data acquisition, data processing, data storage and/or data display (28, 30, 34, 36, 38, 40, 42, 44, 48, 50) - a synchronous video bus (20) interconnecting all of said devices for communicating digital image information therebetween at vide data rates; - a low speed bus interconnecting said devices for communicating control information therebetween; characterized in that - said video bus comprising a time-multiplexed address selection bus, a timing and synchronization bus, and a plurality of N dynamically allocatable data sub-buses; - said address selection bus and each of said data sub-buses comprising a plurality of parallel data lines; - system clock means for producing a periodic signal on the clock bus which defines sequential time slots (BSYSCK); - packet clock means for producing a periodic signal on the clock bus which defines sequential packet slots, each of said packet slots comprising at least N time slots and being synchronized therewith (BPACKETCK); - each of said devices comprising means for transmitting and/or receiving a packet of N serial words of data on each of one or more allocated sub-buses during a packet slot and in synchronization with said time slots; - each of said devices further comprises means for transmitting and/or receiving a single word of address information during a single allocated time slot in each packet which time slot is uniquely allocated (VADDVAL) with the data sub-bus allocated to the device; - whereby said sub-buses are spatially multiplexed among said processes and said address bus is time-multiplexed among a plurality of processes executable in respective device stations.

Claim 3

Dependent Claim 51 words

The apparatus of Claim 1 wherein a device capable of receiving data on a sub-bus further comprises a buffer for intermediately storing data received from said bus during any time slot which occurs during the packet slot prior to the time slot in which address information is transmitted for said device.

Claim 4

Dependent Claim 22 words

The apparatus of Claim 1 in which said D data lines can be subdivided into various words increments of D/N data lines.

Claim 5

Dependent Claim 27 words

The apparatus of Claim 1 wherein where there are D/N data sub-buses and the number of processes which can utilize said bus ranges from 1 to N.

Claim 6

Dependent Claim 22 words

The apparatus of Claim 1 wherein the length of a packet is N words for N sub-buses of D/N data lines each.

Claim 7

Dependent Claim 234 words

An intercommunication bus apparatus for use in an image processing apparatus as claimed in any of Claims 1 to 5, characterized in that the bus apparatus comprises: - D data lines for the transfer of data, said data lines constituting a data bus; - A address lines for addressing data in said device stations; - V video control lines for video control signals; - C collision protection lines for collision protection signals; - a system clock defining time slots for timing system operations; - a packet clock defining multiple time slots for data transfer; - said data bus being divided into N sub-buses, each sub-bus having D/N data lines; - means to allocate said sub-buses to from 1 to N processes, such that each process has an independent data path having one or more sub-buses, depending on the throughput requirements of the process; - means to time-multiplex the addresses of said data sub-buses on said address bus such that each sub-bus address is transferred during a different clock cycle; - each of said addresses accessing N words which are transferred serially, one word per clock cycle on the allocated data sub-bus; - said N words accessed by one address being a data packet; - such that in N clock cycles said bus can transfer N addresses and N data packets, thus completely filling the transfer capacity on said data lines and said address lines.

Claim 8

Dependent Claim 265 words

An intercommunication bus apparatus for use in an image processing apparatus as claimed in any of the Claims 1 to 5, characterized in that the bus apparatus comprises: - D data lines forming a data bus for the transfer of data from one system station to any other system station; - A address lines forming an address bus for addressing data; - a system clock for timing bus operations; - a packet clock for timing the serial transfer of packets of data over said data bus; - a plurality of video control signals transferred over video lines of said bus; - a plurality of collision protection signals transferred over control lines of said bus; - means to divide said data bus into N data sub-buses; - means to allocate from 1 to N of said data sub-buses to from 1 to N processes in the respective stations, such that said data bus is fully utilized when N of said processes are operational; - means to allocate read and write processes to separate read and write data sub-buses; - means to time-multiplex addresses of said data sub-buses on said address bus, by transferring each of said addresses during a different clock cycle of said system clock; - each of said addresses accessing N data words, which data words are transferred serially at a rate of one word per system clock on the corresponding data sub-bus; - said N words accessed by one address being a packet; and - N packets being transferred in the same N system clock cycles during which N data buses are addressed.

Claim 9

Dependent Claim 19 words

The bus apparatus of Claim 7 wherein the means to allocate sub-buses and processes is under control of software.

Image processing apparatus and intercommunication bus therefor

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