Patent US5663578A successfully refreshed from Google Patents.
US5663578A
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Thin film transistor with self-aligned bottom gate
Assignee: International Business Machines Corp
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Filing: 1996-08-02
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Granted: 1997-09-02
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Expires: 2016-08-02
Abstract
Abstract A simple method of making a thin film transistor (TFT) on a substrate with an insulating surface layer is disclosed. A layer of dopant source layer is deposited on the insulating layer, followed by defining a gate stack consisting of a gate polysilicon, gate insulator and a protective polysilicon using the dopant source layer as an etch stop. Sidewall spacers are formed in contact with the gate stack. A TFT body polysilicon is deposited and patterned, forming thereby the source and drain regions in a self-aligned manner. By heating, the dopants from the dopant source layer are driven into the source/drain and to part of the off-set regions of the body polysilicon layer while simultaneously also doping the gate polysilicon.
Inventors
- 👤 Louis Lu-Chen Hsu
- 👤 Mary Joseph Saccamango
- 👤 Joseph Francis Shepard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:55
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0316; H10D30/0321; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/6729; H10D30/673; H10D30/6737; H10D30/6739
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
134 words
A thin film transistor comprising: a dopant source layer on top of a substrate; a doped gate electrode overlying and in contact with said dopant source layer; a gate insulator overlying and in contact with said gate electrode; an insulating sidewall spacers with at least two sides and a bottom, with the bottom in contact with the dopant source layer, and one side adjacent and in contact with at least the sidewalls of the gate electrode and gate insulator; and, a polysilicon body layer, having a doped source, a doped drain, a channel and an off-set regions wherein the source and drain regions are overlying and in contact with the dopant source layer, the channel region is overlying and in contact with said gate insulator, said off-set regions in contact with said sidewall spacer.
Claim 2
Dependent Claim
134 words
A thin film transistor comprising: a dopant source layer on top of a substrate; a doped gate electrode overlying and in contact with said dopant source layer; a gate insulator overlying and in contact with said gate electrode; an insulating sidewall spacers with at least two sides and a bottom, with the bottom in contact with the dopant source layer, and one side adjacent and in contact with at least the sidewalls of the gate electrode and gate insulator; and, a polysilicon body layer, having a doped source, a doped drain, a channel and an off-set regions wherein the source and drain regions are overlying and in contact with the dopant source layer, the channel region is overlying and in contact with said gate insulator, said off-set regions in contact with said sidewall spacer.
Claim 3
Dependent Claim
13 words
The transistor of claim 1, wherein said dopant source layer is borosilicate glass.
Claim 4
Dependent Claim
18 words
The transistor of claim 2, wherein said borosilicate glass contains 2-20 weight percent B 2 O 3 .
Claim 5
Dependent Claim
13 words
The transistor of claim 1, wherein said dopant source layer is phosphosilicate glass.
Claim 6
Dependent Claim
18 words
The transistor of claim 4, wherein said phosphosilicate glass contains 2-10 weight percent P 2 O 5 .
Claim 7
Dependent Claim
23 words
The transistor of claim 1, wherein said gate electrode is polysilicon having a thickness in the range of 100 Å to 2500 Å.
Claim 8
Dependent Claim
13 words
The transistor of claim 1, wherein said gate insulator layer is silicon dioxide.
Claim 9
Dependent Claim
20 words
The transistor of claim 1, wherein said gate insulator layer has a thickness in the range of 100 Å-500 Å.
Claim 10
Dependent Claim
31 words
The transistor of claim 1, wherein said sidewall spacer is formed of at least one layer, selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride and boron nitride.
Claim 11
Dependent Claim
28 words
The transistor of claim 1, wherein said gate electrode, source and drain regions are doped with impurities selected from the group consisting of boron, phosphorus, arsenic and antimony.
Claim 12
Dependent Claim
27 words
The transistor of claim 1, wherein said gate electrode, source and drain regions are doped with impurities in the range of 10 19 to 10 21 .
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-01 | 2001-03-03 | 2001-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-01 | 2005-03-03 | 2005-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-01 | 2009-03-03 | 2009-09-02 | $7700.00 | Window Closed / Lapsed |