US5661692A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Read/write dual port memory having an on-chip input data register
Assignee: Texas Instruments Inc
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Filing: 1995-06-07
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Granted: 1997-08-26
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Expires: 2015-06-07
Abstract
Abstract A dual-port memory having an on-chip color register for storage of input data for use in multiple write cycles is disclosed. The color register is written to during a special cycle, which is enabled by a special function pin in conjunction with the write enable and transfer enable function pins, each of which have their logic state latched in during the row address strobe signal. A second type of special cycle causes a multiplexer to select the contents of the color register, rather than the latched data state of the data input terminals, for the data to be written to the selected memory cells. The use of the color register may be used in conjunction with a mask register, where the writing of certain input/outputs is inhibited. In addition, a block write feature may be incorporated with the color register so that, in another type of special cycle, multiple columns per input/output can be simultaneously written with the contents of the color register. The dual port memory containing the color register thus may rapidly store a bit-mapped graphical image where areas of the image are "filled" with the same color information.
Inventors
- 👤 Raymond Pinkham
- 👤 Anthony M. Balistreri
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 06:37
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1078; G11C7/109; G11C7/1015; G11C7/1039; G11C7/1075; G11C7/1087; G11C7/1093; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
151 words
A memory device comprising: an array of memory cells addressable by rows and columns; random access port circuits for accessing memory cells in said array on a random basis responsive to received control signals and row and column address signals; and serial access port circuits for accessing memory cells in said array on a plural-bit serial basis responsive to received control signals and to row and column address signals, said serial access port circuits including data register circuits having plural bit positions for transferring data in parallel to and from said array and including serial input/output buffer circuits communicating data between an associated serial input/output terminal and said data register circuits, said serial access port circuits including pointer circuits connected between said data register circuits and said buffer circuits, said pointer circuits pointing to sequential bit positions in said data register circuits for connection of sequential bits to said buffer circuits.
Claim 2
Dependent Claim
151 words
A memory device comprising: an array of memory cells addressable by rows and columns; random access port circuits for accessing memory cells in said array on a random basis responsive to received control signals and row and column address signals; and serial access port circuits for accessing memory cells in said array on a plural-bit serial basis responsive to received control signals and to row and column address signals, said serial access port circuits including data register circuits having plural bit positions for transferring data in parallel to and from said array and including serial input/output buffer circuits communicating data between an associated serial input/output terminal and said data register circuits, said serial access port circuits including pointer circuits connected between said data register circuits and said buffer circuits, said pointer circuits pointing to sequential bit positions in said data register circuits for connection of sequential bits to said buffer circuits.
Claim 3
Dependent Claim
35 words
The device of claim 1 in which said pointer circuits include a counter-decoder set to a start bit position, and said counter-decoder is toggled by an external clock signal to increment on each serial cycle.
Claim 4
Dependent Claim
82 words
A process of writing data from a data processing unit to an array of a memory device having a random access port and a serial access port, said process comprising the steps of: transferring data from said data processing unit to a register, in said device and separate from said array, through said random access port; and writing said data in said register to randomly accessed locations in said array responsive to random access address signals produced by said data processing unit.
Claim 5
Dependent Claim
82 words
A process of writing data from a data processing unit to an array of a memory device having a random access port and a serial access port, said process comprising the steps of: transferring data from said data processing unit to a register, in said device and separate from said array, through said random access port; and writing said data in said register to randomly accessed locations in said array responsive to random access address signals produced by said data processing unit.
Claim 6
Dependent Claim
18 words
The process of claim 3 including writing said data to plural locations in sequential random address access cycles.
Claim 7
Dependent Claim
118 words
A memory device comprising: an array of memory cells addressable by rows and columns; random access port circuits for accessing memory cells in said array on a random basis in response to received control signals and row and column address signals; serial access port circuits for accessing memory cells in said array on a plural-bit serial basis in response to received control signals and row and column addresses of said memory cells; and special function logic circuits controlling said random address port circuits in accessing said memory cells, said special function logic circuits including at least one special function pin receiving a special function signal indicating a special function to be performed in randomly accessing said memory cells.
Claim 8
Dependent Claim
118 words
A memory device comprising: an array of memory cells addressable by rows and columns; random access port circuits for accessing memory cells in said array on a random basis in response to received control signals and row and column address signals; serial access port circuits for accessing memory cells in said array on a plural-bit serial basis in response to received control signals and row and column addresses of said memory cells; and special function logic circuits controlling said random address port circuits in accessing said memory cells, said special function logic circuits including at least one special function pin receiving a special function signal indicating a special function to be performed in randomly accessing said memory cells.
Claim 9
Dependent Claim
38 words
The device of claim 5 in which said special function logic circuits decode said special function from said special function signal and said control signals to effect special functions including mask write, block write, and color register write.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-25 | 2001-02-24 | 2001-08-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-25 | 2005-02-24 | 2005-08-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-25 | 2009-02-24 | 2009-08-26 | $7700.00 | Window Closed / Lapsed |