Dual-port semiconductor memory device

Claim 1

A dual-port semiconductor memory device comprising: a row address decoder, receiving a row address, for decoding the row address; a column address decoder, receiving a column address, for decoding the column address; a plurality of bit lines including n bit line pairs, where n is an integer; a plurality of word lines intersecting said bit lines; a memory cell array comprising an array of memory cells formed at the intersections of word lines and bit lines, a specific word line being selected in response to the decoded row address from said row address decoder; a first transfer gate means coupled to said n bit line pairs, for selecting at least one of said n bit line pairs in response to the decoded column address from said column address decoder; a first pair of data buses coupled to said first transfer gate means; a first port coupled to said first pair of data buses; sense amplifier means, connected between said n bit line pairs, for sensing and amplifying a potential difference between two bit lines in each of said n bit line pairs; second transfer gate means coupled to said sense amplifier means; serial access memory means coupled to said second transfer gate means; said second transfer gate means selectively coupling groups of n/m bit line pairs to said serial access memory means through said sense amplifier means in n/m sequential stages, where m is an integer smaller than n and each of said groups of n/m bit line pairs are formed by m different bit line pairs; third transfer gate means coupled to said serial access memory means; a second pair of data buses coupled to said serial access memory means through said third transfer gate means; said third transfer gate means sequentially coupling the m bit line pairs in each of said groups of bit line pairs to said second pair of data buses in each of said n/m stages through said sense amplifier means and said second transfer gate means; and a second port coupled to said second pair of data buses.