Patent US5659715A successfully refreshed from Google Patents.
US5659715A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for allocating display memory and main memory employing access request arbitration and buffer control
Assignee: Philips Semiconductors Inc
•
Filing: 1996-05-08
•
Granted: 1997-08-19
•
Expires: 2016-05-08
Abstract
Abstract A low-cost, moderate performance small computer system is provided by allowing a single sharable block of memory to be independently accessible as graphics or main store memory. Allocation of the memory is selected programmably, eliminating the need to have the maximum memory size for each block simultaneously. Performance penalties are minimized by dynamically allocating the memory bandwidth on demand rather than through fixed time slices. A reallocatable memory subsystem enables transparent transfer of memory function of a lower-performance memory such as DRAM to occur in conjunction with a memory upgrade to a higher-performance memory such as VRAM, for example.
Inventors
- 👤 Shih-Ho Wu
- 👤 William Desi Rhoden
- 👤 Mike Nakahara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:42
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/18; G09G2360/00; G09G2360/12; G09G2360/125; G09G5/363
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
78 words
For use in a computing apparatus including a CPU and a first memory allocated as display memory, the apparatus comprising: memory slots; configuration means responsive to a second memory having a different performance level than said first memory being added to said memory slots for thereafter, at power-up, automatically allocating said second memory as display memory and said first memory as main memory; and means for allowing substantially independent access to said first memory and said second memory.
Claim 2
Dependent Claim
78 words
For use in a computing apparatus including a CPU and a first memory allocated as display memory, the apparatus comprising: memory slots; configuration means responsive to a second memory having a different performance level than said first memory being added to said memory slots for thereafter, at power-up, automatically allocating said second memory as display memory and said first memory as main memory; and means for allowing substantially independent access to said first memory and said second memory.
Claim 3
Dependent Claim
141 words
The apparatus of claim 1 further comprising: memory controller means for controlling access to said first and second memories, including arbitration means for arbitrating among a plurality of requests for access to said first and second memories; first data path means connected to said arbitration means and including first buffer storage means for facilitating exchange of data with said first memory; second data path means connected to said arbitration means and including second buffer storage means for facilitating exchange of data with said second memory; and control means connected to said configuration means and responsive to at least one of a plurality of signals applied to said apparatus, said signals including address, data and control signals, for causing a plurality of signal from among said data signals to be applied to only one of said first and second data path means.
Claim 4
Dependent Claim
13 words
The apparatus of claim 2 wherein said control means comprises a bus controller.
Claim 5
Dependent Claim
15 words
The apparatus of claim 3 wherein said first buffer storage means comprises a system queue.
Claim 6
Dependent Claim
27 words
The apparatus of claim 4 wherein said first buffer storage means further comprises a system queue controller connected to said system queue and to said bus controller.
Claim 7
Independent Claim
87 words
A method of increasing the performance of a computing apparatus including a CPU, memory slots, and a first memory allocated as display memory, comprising the steps of: adding to said memory slots a second memory having a different performance level than said first memory; thereafter, at power-up, automatically allocating said second memory as display memory only and changing allocation of said first memory such that said first memory is allocated as main memory only; and allowing substantially independent access to said first memory and said second memory.
Claim 8
Independent Claim
87 words
A method of increasing the performance of a computing apparatus including a CPU, memory slots, and a first memory allocated as display memory, comprising the steps of: adding to said memory slots a second memory having a different performance level than said first memory; thereafter, at power-up, automatically allocating said second memory as display memory only and changing allocation of said first memory such that said first memory is allocated as main memory only; and allowing substantially independent access to said first memory and said second memory.
References Cited (Backward Citations)
US4028663A
Cited
US4277836A
Cited
EP0217479A2
Cited
US4608632A
Cited
US5165103A
Cited
US5157774A
Cited
US4910687A
Cited
US4953101A
Cited
US5384900A
Cited
US5276848A
Cited
US5081699A
Cited
US4980828A
Cited
US5126910A
Cited
US5376949A
Cited
US5276851A
Cited
US5117243A
Cited
US5361387A
Cited
US5293483A
Cited
US5291604A
Cited
US5229758A
Cited
US5357628A
Cited
US5335322A
Cited
US5265218A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-18 | 2001-02-17 | 2001-08-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-18 | 2005-02-17 | 2005-08-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-18 | 2009-02-17 | 2009-08-19 | $7700.00 | Window Closed / Lapsed |