Cache coherency in a multiprocessing system

Claim 2

In a data processing system including a plurality of bus devices coupled through a bus architecture with a memory device, a method comprising the steps of: issuing a read operation onto said bus architecture, said read operation issued by a first one of said plurality of bus devices, said read operation configured to read a data portion from said memory device; snooping of said read operation by a second one of said plurality of bus devices; determining, by said second one of said plurality of bus devices, if a modified copy of said data portion is contained within said second one of said plurality of bus devices; sending, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus device determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, a signal that causes said first one of said plurality of bus devices to ignore any other version of said data portion received by said first one of said plurality of bus devices from said memory device; and sending a message, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus devices determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, indicating that said modified copy of said data portion is contained within said second one of said plurality of bus devices, said message sent in parallel with said signal.

Claim 3

The method as recited in claim 1, further comprising the step of: sending a copy of said modified copy of said data portion from said second one of said plurality of bus devices to a cache of said first one of said plurality of bus device, said copy of said modified copy of said data portion following said signal.

Claim 4

The method as recited in claim 2, further comprising the step of: receiving, by said first one of said plurality of bus devices, said copy of said modified copy of said data portion, wherein receipt, by said first one of said plurality of bus devices, of said copy of said modified copy of said data portion takes priority over receipt of said data portion from said memory device.

Claim 5

The method as recited in claim 3, further comprising the step of: ignoring, by said first one of said plurality of bus devices, said data portion received from said memory device.

Claim 6

The method as recited in claim 2, wherein said data processing system further includes a system controller coupled point-to-point to each of said bus devices, and wherein said step of sending said copy of said modified copy of said data portion from said second one of said plurality of bus devices to said first one of said plurality of bus devices further comprises the steps of: transmitting, from said second one of said plurality of bus devices to said system controller, a data-only bus request; and returning, from said system controller to said second one of said plurality of bus devices, a bus grant in response to said data-only bus request, said transmitting and said returning steps occurring before said step of sending said copy of said modified copy of said data portion from said second one of said plurality of bus devices to said first one of said plurality of bus devices.

Claim 7

The method as recited in claim 2, further comprising the step of: sending said copy of said modified copy of said data portion from said second one of said plurality of bus devices to said memory device.

Claim 8

The method as recited in claim 1, wherein said read operation is a read-with-intent-to-modify operation.

Claim 9

The method as recited in claim 1, wherein said copy of said modified copy of said data portion is received by said first one of said plurality of bus devices from said second one of said plurality of bus devices with said signal before said message is received by said first one of said plurality of bus devices.

Claim 10

The method as recited in claim 8, wherein said first one of said plurality of bus devices does not accept said copy of said modified copy of said data portion received from said second one of said plurality of bus devices if said signal is not asserted.

Claim 11

The method as recited in claim 8, wherein said first one of said plurality of bus devices will accept said copy of said modified copy of said data portion if said signal is asserted even though said message has not yet been received by said first one of said plurality of bus devices.

Claim 12

A data processing system, comprising: a plurality of bus devices; a bus configured in a predetermined architecture; a memory device, wherein said bus couples said plurality of bus devices and said memory device, wherein said plurality of bus devices comprises one or more processors; means, coupled to a first one of said plurality of bus devices, for issuing a read operation onto said bus architecture, said read operation issued by said first one of said plurality of bus devices, said read operation configured to read a data portion from said memory device; means, coupled to a second one of said plurality of bus devices, for snooping of said read operation by said second one of said plurality of bus devices; means, coupled to said second one of said plurality of bus devices, for determining, by said second one of said plurality of bus devices, if a modified copy of said data portion is contained within said second one of said plurality of bus devices; means, coupled to said second one of said plurality of bus devices, for sending, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus devices determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, a signal that causes said first one of said plurality of bus devices to ignore any other version of said data portion received by said first one of said plurality of bus devices from said memory device; and means, coupled to said second one of said plurality of bus devices, for sending a message, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus devices determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, indicating that said modified copy of said data portion is contained within said second one of said plurality of bus devices, said message sent in parallel with said signal.

Claim 13

A data processing system, comprising: a plurality of bus devices; a bus configured in a predetermined architecture; a memory device, wherein said bus couples said plurality of bus devices and said memory device, wherein said plurality of bus devices comprises one or more processors; means, coupled to a first one of said plurality of bus devices, for issuing a read operation onto said bus architecture, said read operation issued by said first one of said plurality of bus devices, said read operation configured to read a data portion from said memory device; means, coupled to a second one of said plurality of bus devices, for snooping of said read operation by said second one of said plurality of bus devices; means, coupled to said second one of said plurality of bus devices, for determining, by said second one of said plurality of bus devices, if a modified copy of said data portion is contained within said second one of said plurality of bus devices; means, coupled to said second one of said plurality of bus devices, for sending, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus devices determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, a signal that causes said first one of said plurality of bus devices to ignore any other version of said data portion received by said first one of said plurality of bus devices from said memory device; and means, coupled to said second one of said plurality of bus devices, for sending a message, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus devices determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, indicating that said modified copy of said data portion is contained within said second one of said plurality of bus devices, said message sent in parallel with said signal.

Claim 14

The system as recited in claim 11, comprising: means, coupled to said second one of said plurality of bus devices, for sending a copy of said modified copy of said data portion from a cache of said second one of said plurality of bus devices to a cache of said first one of said plurality of bus devices, said copy of said modified of said data portion following said signal.

Claim 15

The system as recited in claim 12, further comprising: means for receiving, by said first one of said plurality of bus devices, said copy of said modified copy of said data portion, wherein receipt, by said first one of said plurality of bus devices, of said copy of said modified copy of said data portion takes priority over receipt of said data portion from said memory device.

Claim 16

The system as recited in claim 13, further comprising: means for ignoring, by said first one of said plurality of bus devices, said data portion received from said memory device.

Claim 17

The system as recited in claim 11, wherein said read operation is a read-with-intent-to-modify operation.

Claim 18

The system as recited in claim 11, wherein said plurality of bus devices further includes one or more I/O channel controllers coupled to an I/O bus, and wherein said memory device includes a memory controller coupled to a storage device.

Claim 19

In a data processing system including a plurality of bus devices coupled through a bus architecture with a memory device, a method comprising the steps of: issuing a read operation onto said bus architecture, said read operation issued by a first one of said plurality of bus devices, said read operation configured to read a data portion from said memory device: snooping of said read operation by a second one of said plurality of bus devices; determining, by said second one of said plurality of bus devices, if a modified copy of said data portion is contained within said second one of said plurality of bus devices; and sending, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus device determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, a signal that causes said first one of said plurality of bus devices to ignore any other version of said data portion received by said first one of said plurality of bus devices from said memory device, wherein said data processing system further includes a system controller coupled point-to-point with each of said bus devices, further comprising the steps of: transmitting a bus request for said read operation by said first one of said plurality of bus devices to said system controller; and returning, from said system controller to said first one of said plurality of bus devices, a bus grant for said read operation in response to said bus request, said transmitting and said returning steps occurring before said issuing step.

Claim 20

In a data processing system including a plurality of bus devices coupled through a bus architecture with a memory device, a method comprising the steps of: issuing a read operation onto said bus architecture, said read operation issued by a first one of said plurality of bus devices, said read operation configured to read a data portion from said memory device: snooping of said read operation by a second one of said plurality of bus devices; determining, by said second one of said plurality of bus devices, if a modified copy of said data portion is contained within said second one of said plurality of bus devices; and sending, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus device determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, a signal that causes said first one of said plurality of bus devices to ignore any other version of said data portion received by said first one of said plurality of bus devices from said memory device, wherein said data processing system further includes a system controller coupled point-to-point with each of said bus devices, further comprising the steps of: transmitting a bus request for said read operation by said first one of said plurality of bus devices to said system controller; and returning, from said system controller to said first one of said plurality of bus devices, a bus grant for said read operation in response to said bus request, said transmitting and said returning steps occurring before said issuing step.

Claim 21

A data processing system, comprising: a plurality of bus devices; a bus configured in a predetermined architecture; a memory device, wherein said bus couples said plurality of bus devices and said memory device, wherein said plurality of bus devices comprises one or more processors; means, coupled to a first one of said plurality of bus devices, for issuing a read operation onto said bus architecture, said read operation issued by said first one of said plurality of bus devices, said read operation configured to read a data portion from said memory device; means, coupled to a second one of said plurality of bus devices, for snooping of said read operation by said second one of said plurality of bus devices; means, coupled to said second one of said plurality of bus devices, for determining, by said second one of said plurality of bus devices, if a modified copy of said data portion is contained within said second one of said plurality of bus devices; and means, coupled to said second one of said plurality of bus devices, for sending, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus devices determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, a signal that causes said first one of said plurality of bus devices to ignore any other version of said data portion received by said first one of said plurality of bus devices from said memory device, wherein said data processing system further includes a system controller coupled point-to-point with each of said bus devices, further comprising: means, coupled to said first one of said plurality of bus devices, for transmitting a bus request for said read operation by said first one of said plurality of bus devices to said system controller; and means, coupled to said system controller, for returning, from said system controller to said first one of said plurality of bus devices, a bus grant for said read operation in response to said bus request.

Claim 22

A data processing system, comprising: a plurality of bus devices; a bus configured in a predetermined architecture; a memory device, wherein said bus couples said plurality of bus devices and said memory device, wherein said plurality of bus devices comprises one or more processors; means, coupled to a first one of said plurality of bus devices, for issuing a read operation onto said bus architecture, said read operation issued by said first one of said plurality of bus devices, said read operation configured to read a data portion from said memory device; means, coupled to a second one of said plurality of bus devices, for snooping of said read operation by said second one of said plurality of bus devices; means, coupled to said second one of said plurality of bus devices, for determining, by said second one of said plurality of bus devices, if a modified copy of said data portion is contained within said second one of said plurality of bus devices; and means, coupled to said second one of said plurality of bus devices, for sending, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus devices determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, a signal that causes said first one of said plurality of bus devices to ignore any other version of said data portion received by said first one of said plurality of bus devices from said memory device, wherein said data processing system further includes a system controller coupled point-to-point with each of said bus devices, further comprising: means, coupled to said first one of said plurality of bus devices, for transmitting a bus request for said read operation by said first one of said plurality of bus devices to said system controller; and means, coupled to said system controller, for returning, from said system controller to said first one of said plurality of bus devices, a bus grant for said read operation in response to said bus request.

Claim 23

A data processing system, comprising: a plurality of bus devices; a bus configured in a predetermined architecture; a memory device, wherein said bus couples said plurality of bus devices and said memory device, wherein said plurality of bus devices comprises one or more processors; means, coupled to a first one of said plurality of bus devices, for issuing a read operation onto said bus architecture, said read operation issued by said first one of said plurality of bus devices, said read operation configured to read a data portion from said memory device; means, coupled to a second one of said plurality of bus devices, for snooping of said read operation by said second one of said plurality of bus devices; means, coupled to said second one of said plurality of bus devices, for determining, by said second one of said plurality of bus devices, if a modified copy of said data portion is contained within said second one of said plurality of bus devices; means, coupled to said second one of said plurality of bus devices, for sending, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus devices determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, a signal that causes said first one of said plurality of bus devices to ignore any other version of said data portion received by said first one of said plurality of bus devices from said memory device; means, coupled to said second one of said plurality of bus devices, for sending a message, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus devices determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, indicating that said modified copy of said data portion is contained within said second one of said plurality of bus devices, said message sent in parallel with said signal; and means, coupled to said second one of said plurality of bus devices, for sending said copy of said modified copy of said data portion from a cache of said second one of said plurality of bus devices to a cache of said first one of said plurality of bus devices, said copy of said modified copy of said data portion following said signal indicating that data being sent is a copy of said modified copy of said data portion, wherein said data processing system further includes a system controller coupled point-to-point to each of said bus devices, and wherein said means for sending of said copy of said modified copy of said data portion from said second one of said plurality of bus devices to said first one of said plurality of bus devices further comprises: means for transmitting, from said second one of said plurality of bus devices to said system controller, a data-only bus request; and means for returning, from said system controller to said second one of said plurality of bus devices, a bus grant in response to said data-only bus request.

Claim 24

A data processing system, comprising: a plurality of bus devices; a bus configured in a predetermined architecture; a memory device, wherein said bus couples said plurality of bus devices and said memory device, wherein said plurality of bus devices comprises one or more processors; means, coupled to a first one of said plurality of bus devices, for issuing a read operation onto said bus architecture, said read operation issued by said first one of said plurality of bus devices, said read operation configured to read a data portion from said memory device; means, coupled to a second one of said plurality of bus devices, for snooping of said read operation by said second one of said plurality of bus devices; means, coupled to said second one of said plurality of bus devices, for determining, by said second one of said plurality of bus devices, if a modified copy of said data portion is contained within said second one of said plurality of bus devices; means, coupled to said second one of said plurality of bus devices, for sending, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus devices determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, a signal that causes said first one of said plurality of bus devices to ignore any other version of said data portion received by said first one of said plurality of bus devices from said memory device; means, coupled to said second one of said plurality of bus devices, for sending a message, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus devices determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, indicating that said modified copy of said data portion is contained within said second one of said plurality of bus devices, said message sent in parallel with said signal; and means, coupled to said second one of said plurality of bus devices, for sending said copy of said modified copy of said data portion from a cache of said second one of said plurality of bus devices to a cache of said first one of said plurality of bus devices, said copy of said modified copy of said data portion following said signal indicating that data being sent is a copy of said modified copy of said data portion, wherein said data processing system further includes a system controller coupled point-to-point to each of said bus devices, and wherein said means for sending of said copy of said modified copy of said data portion from said second one of said plurality of bus devices to said first one of said plurality of bus devices further comprises: means for transmitting, from said second one of said plurality of bus devices to said system controller, a data-only bus request; and means for returning, from said system controller to said second one of said plurality of bus devices, a bus grant in response to said data-only bus request.

Claim 25

A data processing system, comprising: a plurality of bus devices; a bus configured in a predetermined architecture; a memory device, wherein said bus couples said plurality of bus devices and said memory device, wherein said plurality of bus devices comprises one or more processors; means, coupled to a first one of said plurality of bus devices, for issuing a read operation onto said bus architecture, said read operation issued by said first one of said plurality of bus devices, said read operation configured to read a data portion from said memory device; means, coupled to a second one of said plurality of bus devices, for snooping of said read operation by said second one of said plurality of bus devices; means, coupled to said second one of said plurality of bus devices, for determining, by said second one of said plurality of bus devices, if a modified copy of said data portion is contained within said second one of said plurality of bus devices; means, coupled to said second one of said plurality of bus devices, for sending, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus devices determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, a signal that causes said first one of said plurality of bus devices to ignore any other version of said data portion received by said first one of said plurality of bus devices from said memory device; means, coupled to said second one of said plurality of bus devices, for sending a message, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus devices determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, indicating that said modified copy of said data portion is contained within said second one of said plurality of bus devices, said message sent in parallel with said signal; and means, coupled to said second one of said plurality of bus devices, for sending said copy of said modified copy of said data portion from a cache of said second one of said plurality of bus devices to a cache of said first one of said plurality of bus devices, said copy of said modified copy of said data portion following said signal indicating that data being sent is a copy of said modified copy of said data portion, further comprising: means, coupled to said second one of said plurality of bus devices, for sending said copy of said modified copy of said data portion from said second one of said plurality of bus devices to said memory device.

Claim 26

A data processing system, comprising: a plurality of bus devices; a bus configured in a predetermined architecture; a memory device, wherein said bus couples said plurality of bus devices and said memory device, wherein said plurality of bus devices comprises one or more processors; means, coupled to a first one of said plurality of bus devices, for issuing a read operation onto said bus architecture, said read operation issued by said first one of said plurality of bus devices, said read operation configured to read a data portion from said memory device; means, coupled to a second one of said plurality of bus devices, for snooping of said read operation by said second one of said plurality of bus devices; means, coupled to said second one of said plurality of bus devices, for determining, by said second one of said plurality of bus devices, if a modified copy of said data portion is contained within said second one of said plurality of bus devices; means, coupled to said second one of said plurality of bus devices, for sending, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus devices determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, a signal that causes said first one of said plurality of bus devices to ignore any other version of said data portion received by said first one of said plurality of bus devices from said memory device; means, coupled to said second one of said plurality of bus devices, for sending a message, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus devices determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, indicating that said modified copy of said data portion is contained within said second one of said plurality of bus devices, said message sent in parallel with said signal; and means, coupled to said second one of said plurality of bus devices, for sending said copy of said modified copy of said data portion from a cache of said second one of said plurality of bus devices to a cache of said first one of said plurality of bus devices, said copy of said modified copy of said data portion following said signal indicating that data being sent is a copy of said modified copy of said data portion, further comprising: means, coupled to said second one of said plurality of bus devices, for sending said copy of said modified copy of said data portion from said second one of said plurality of bus devices to said memory device.

Claim 27

In a data processing system including a plurality of bus devices coupled through a bus architecture with a memory device, and a system controller coupled point-to-point with each of said bus devices, wherein each of said plurality of bus devices includes a cache, a method comprising the steps of: transmitting a bus request for a read operation by a first one of said plurality of bus devices to said system controller; returning, from said system controller to said first one of said plurality of bus devices, a bus grant for said read operation in response to said bus request; issuing a read operation onto said bus architecture, said read operation issued by said first one of said plurality of bus devices, said read operation configured to read a data portion from said memory device; snooping of said read operation by a second one of said plurality of bus devices; determining, by said second one of said plurality of bus devices, if a modified copy of said data portion is contained within a cache of said second one of said plurality of bus devices; sending a message, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus devices determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, indicating that said modified copy of said data portion is contained within said second one of said plurality of bus devices; transmitting, from said second one of said plurality of bus devices to said system controller, a data-only bus request; returning, from said system controller to said second one of said plurality of bus devices, a bus grant in response to said data-only bus request; sending, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus devices determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, a signal that causes said first one of said plurality of bus devices to ignore any other version of said data portion received by said first one of said plurality of bus devices from said memory device; sending said copy of said modified copy of said data portion from said second one of said plurality of bus devices to a cache of said first one of said plurality of bus devices, said copy of said modified copy of said data portion following said signal, said transmitting and said remaining steps occurring before said step of sending said copy of said modified copy of said data portion from said second one of said plurality of bus devices to said first one of said plurality of bus devices; and receiving, by said first one of said plurality of bus devices, said copy of said modified copy of said data portion, wherein receipt, by said first one of said plurality of bus devices, of said copy of said modified copy of said data portion takes priority over receipt of said data portion from said memory device.

Claim 28

In a data processing system including a plurality of bus devices coupled through a bus architecture with a memory device, and a system controller coupled point-to-point with each of said bus devices, wherein each of said plurality of bus devices includes a cache, a method comprising the steps of: transmitting a bus request for a read operation by a first one of said plurality of bus devices to said system controller; returning, from said system controller to said first one of said plurality of bus devices, a bus grant for said read operation in response to said bus request; issuing a read operation onto said bus architecture, said read operation issued by said first one of said plurality of bus devices, said read operation configured to read a data portion from said memory device; snooping of said read operation by a second one of said plurality of bus devices; determining, by said second one of said plurality of bus devices, if a modified copy of said data portion is contained within a cache of said second one of said plurality of bus devices; sending a message, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus devices determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, indicating that said modified copy of said data portion is contained within said second one of said plurality of bus devices; transmitting, from said second one of said plurality of bus devices to said system controller, a data-only bus request; returning, from said system controller to said second one of said plurality of bus devices, a bus grant in response to said data-only bus request; sending, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus devices determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, a signal that causes said first one of said plurality of bus devices to ignore any other version of said data portion received by said first one of said plurality of bus devices from said memory device; sending said copy of said modified copy of said data portion from said second one of said plurality of bus devices to a cache of said first one of said plurality of bus devices, said copy of said modified copy of said data portion following said signal, said transmitting and said remaining steps occurring before said step of sending said copy of said modified copy of said data portion from said second one of said plurality of bus devices to said first one of said plurality of bus devices; and receiving, by said first one of said plurality of bus devices, said copy of said modified copy of said data portion, wherein receipt, by said first one of said plurality of bus devices, of said copy of said modified copy of said data portion takes priority over receipt of said data portion from said memory device.

Claim 29

In a data processing system including a plurality of bus devices coupled through a bus architecture with a memory device, a method comprising the steps of: issuing a read operation onto said bus architecture, said read operation issued by a first one of said plurality of bus devices, said read operation configured to read a data portion from said memory device; snooping of said read operation by a second one of said plurality of bus devices; and determining, by said second one of said plurality of bus devices, if a modified copy of said data portion is contained within said second one of said plurality of bus devices; sending, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus device determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, a signal that causes said first one of said plurality of bus devices to ignore any other version of said data portion received by said first one of said plurality of bus devices from said memory device, wherein said first one of said plurality of bus devices ignores any data not accompanied by said signal.

Claim 30

In a data processing system including a plurality of bus devices coupled through a bus architecture with a memory device, a method comprising the steps of: issuing a read operation onto said bus architecture, said read operation issued by a first one of said plurality of bus devices, said read operation configured to read a data portion from said memory device; snooping of said read operation by a second one of said plurality of bus devices; and determining, by said second one of said plurality of bus devices, if a modified copy of said data portion is contained within said second one of said plurality of bus devices; sending, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus device determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, a signal that causes said first one of said plurality of bus devices to ignore any other version of said data portion received by said first one of said plurality of bus devices from said memory device, wherein said first one of said plurality of bus devices ignores any data not accompanied by said signal.

Claim 31

The method as recited in claim 22, wherein said any data is received before said copy of said modified copy of said data portion accompanied by said signal.

Claim 32

A data processing system, comprising: a plurality of bus devices; a bus configured in a predetermined architecture; a memory device, wherein said bus couples said plurality of bus devices and said memory device, wherein said plurality of bus devices comprises one or more processors; means, coupled to a first one of said plurality of bus devices, for issuing a read operation onto said bus architecture, said read operation issued by said first one of said plurality of bus devices, said read operation configured to read a data portion from said memory device; means, coupled to a second one of said plurality of bus devices, for snooping of said read operation by said second one of said plurality of bus devices; means, coupled to said second one of said plurality of bus devices, for determining, by said second one of said plurality of bus devices, if a modified copy of said data portion is contained within said second one of said plurality of bus devices; and means, coupled to said second one of said plurality of bus devices, for sending, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus devices determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, a signal that causes said first one of said plurality of bus devices to ignore any other version of said data portion received by said first one of said plurality of bus devices from said memory device, wherein said first one of said plurality of bus devices ignores any data not accompanied by said signal.

Claim 33

A data processing system, comprising: a plurality of bus devices; a bus configured in a predetermined architecture; a memory device, wherein said bus couples said plurality of bus devices and said memory device, wherein said plurality of bus devices comprises one or more processors; means, coupled to a first one of said plurality of bus devices, for issuing a read operation onto said bus architecture, said read operation issued by said first one of said plurality of bus devices, said read operation configured to read a data portion from said memory device; means, coupled to a second one of said plurality of bus devices, for snooping of said read operation by said second one of said plurality of bus devices; means, coupled to said second one of said plurality of bus devices, for determining, by said second one of said plurality of bus devices, if a modified copy of said data portion is contained within said second one of said plurality of bus devices; and means, coupled to said second one of said plurality of bus devices, for sending, from said second one of said plurality of bus devices to said first one of said plurality of bus devices when said second one of said plurality of bus devices determines that said modified copy of said data portion is contained within said second one of said plurality of bus devices, a signal that causes said first one of said plurality of bus devices to ignore any other version of said data portion received by said first one of said plurality of bus devices from said memory device, wherein said first one of said plurality of bus devices ignores any data not accompanied by said signal.

Claim 34

The system as recited in claim 24, wherein said any data is received before said data portion with said signal.

Claim 35

A data processing system, comprising: a plurality of bus devices, wherein said plurality of bus devices comprises one or more processors; a memory device; a bus connecting said plurality of bus devices and said memory device; circuitry in a first one of said plurality of bus devices for issuing a read operation onto said bus, said read operation issued by said first one of said plurality of bus devices, said read operation configured to read a data portion from said memory device; circuitry in a second one of said plurality of bus devices for snooping of said read operation by said second one of said plurality of bus devices; circuitry in said second one of said plurality of bus devices for determining, by said second one of said plurality of bus devices, if a modified copy of said data portion is contained within said second one of said plurality of bus devices; circuitry in said second one of said plurality of bus devices for sending a message, from said second one of said plurality of bus devices onto said bus, indicating that said modified copy of said data portion is contained within said second one of said plurality of bus devices; circuitry in said second one of said plurality of bus devices for sending said copy of said modified copy of said data portion from a cache of said second one of said plurality of bus devices to a cache of said first one of said plurality of bus devices, along with a bit indicating whether said copy of said modified copy of said data portion is a latest copy of said data portion; circuitry for sending said data portion from said memory device to said first one of said plurality of bus devices; circuitry in said first one of said plurality of bus devices for not accepting said data portion received from said memory device if said bit accompanying said data portion from said memory device is not asserted; and circuitry in said first one of said plurality of bus devices for accepting said copy of said modified copy of said data portion from said second one of said plurality of bus devices if said bit accompanying said copy is asserted even if said message has not yet been received by said first one of said plurality of bus devices.

Claim 36

A data processing system, comprising: a plurality of bus devices, wherein said plurality of bus devices comprises one or more processors; a memory device; a bus connecting said plurality of bus devices and said memory device; circuitry in a first one of said plurality of bus devices for issuing a read operation onto said bus, said read operation issued by said first one of said plurality of bus devices, said read operation configured to read a data portion from said memory device; circuitry in a second one of said plurality of bus devices for snooping of said read operation by said second one of said plurality of bus devices; circuitry in said second one of said plurality of bus devices for determining, by said second one of said plurality of bus devices, if a modified copy of said data portion is contained within said second one of said plurality of bus devices; circuitry in said second one of said plurality of bus devices for sending a message, from said second one of said plurality of bus devices onto said bus, indicating that said modified copy of said data portion is contained within said second one of said plurality of bus devices; circuitry in said second one of said plurality of bus devices for sending said copy of said modified copy of said data portion from a cache of said second one of said plurality of bus devices to a cache of said first one of said plurality of bus devices, along with a bit indicating whether said copy of said modified copy of said data portion is a latest copy of said data portion; circuitry for sending said data portion from said memory device to said first one of said plurality of bus devices; circuitry in said first one of said plurality of bus devices for not accepting said data portion received from said memory device if said bit accompanying said data portion from said memory device is not asserted; and circuitry in said first one of said plurality of bus devices for accepting said copy of said modified copy of said data portion from said second one of said plurality of bus devices if said bit accompanying said copy is asserted even if said message has not yet been received by said first one of said plurality of bus devices.