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US5659183A Expired / Lapsed US ⏱️ 0.0 years remaining

Thin film transistor having a drain offset region

Assignee: Micron Technology Inc
•
Filing: 1996-11-01
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Granted: 1997-08-19
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Expires: 2016-11-01
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Abstract

Abstract A method of forming a thin film transistor of a first conductivity type includes, a) providing a thin film transistor layer of semiconductive material; b) first masking the thin film transistor layer to mask a desired drain offset region while leaving a desired channel region exposed; c) with the first masking in place, doping the exposed channel region with a conductivity enhancing impurity of a second type; d) second masking the thin film transistor layer to mask the channel region and the drain offset region and leave desired opposing source/drain regions exposed; and e) with the second masking in place, doping the exposed source/drain regions with a conductivity enhancing impurity of the first type. A thin film transistor includes, ii) a thin film layer of semiconductive material, the thin film layer comprising a source region, a drain region, a drain offset region and a channel region; the source and drain regions being conductively doped with a conductivity enhancing impurity of the first type to a concentration effective to render such source and drain regions electrically conductive; the channel region being doped with a conductivity enhancing impurity of a second type to a first concentration; the drain offset region being doped with a conductivity enhancing impurity of the second type to a second concentration, the second concentration being less than the first concentration; and ii) a gate positioned operatively adjacent the channel region. Alternately, the drain offset region consists essentially of undoped semiconductive material.

Inventors

  • 👤 Monte Manning
  • 👤 Shubneesh Batra

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 02:31
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0316; H10D30/0321; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/6717; H10D30/6729; H10D30/673; H10D30/6733; H10D30/6734; H10D30/674

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 119 words
A thin film transistor of a first conductivity type comprising: a thin film layer of semiconductive material, the thin film layer comprising a source region, a drain region, a drain offset region and a channel region; the source and drain regions being conductively doped with a conductivity enhancing impurity of the first conductivity type to a concentration effective to render such source and drain regions electrically conductive; the channel region being doped with a conductivity enhancing impurity to a first concentration; the drain offset region being doped with a conductivity enhancing impurity of a second conductivity type to a second concentration, the second concentration being less than the first concentration; and a gate positioned operatively adjacent the channel region.
Claim 2
Dependent Claim 119 words
A thin film transistor of a first conductivity type comprising: a thin film layer of semiconductive material, the thin film layer comprising a source region, a drain region, a drain offset region and a channel region; the source and drain regions being conductively doped with a conductivity enhancing impurity of the first conductivity type to a concentration effective to render such source and drain regions electrically conductive; the channel region being doped with a conductivity enhancing impurity to a first concentration; the drain offset region being doped with a conductivity enhancing impurity of a second conductivity type to a second concentration, the second concentration being less than the first concentration; and a gate positioned operatively adjacent the channel region.
Claim 3
Dependent Claim 38 words
The thin film transistor of claim 1 wherein the conductivity type of the channel region is the second type, the second type conductivity enhancing impurity of the channel region and the drain offset region being the same impurity.
Claim 4
Dependent Claim 21 words
The thin film transistor of claim 1 wherein the first conductivity type is p and the second conductivity type is n.
Claim 5
Dependent Claim 21 words
The thin film transistor of claim 1 wherein the first conductivity type is n and the second conductivity type is p.
Claim 6
Dependent Claim 82 words
A thin film transistor of a first conductivity type comprising: a thin film layer of semiconductive material, the thin film layer comprising a drain offset region and a channel region, the channel region being doped with a conductivity enhancing impurity to a first concentration; the drain offset region being doped with a conductivity enhancing impurity of a second conductivity type to a second concentration, the second concentration being less than the first concentration; and a gate positioned operatively adjacent the channel region.
Claim 7
Dependent Claim 82 words
A thin film transistor of a first conductivity type comprising: a thin film layer of semiconductive material, the thin film layer comprising a drain offset region and a channel region, the channel region being doped with a conductivity enhancing impurity to a first concentration; the drain offset region being doped with a conductivity enhancing impurity of a second conductivity type to a second concentration, the second concentration being less than the first concentration; and a gate positioned operatively adjacent the channel region.
Claim 8
Dependent Claim 45 words
The thin film transistor of claim 5 wherein the conductivity type of the impurity in the channel region is the second conductivity type and wherein the second conductivity type conductivity enhancing impurity of the channel region and the drain offset region are the same impurity.
Claim 9
Dependent Claim 21 words
The thin film transistor of claim 5 wherein the first conductivity type is p and the second conductivity type is n.
Claim 10
Dependent Claim 21 words
The thin film transistor of claim 5 wherein the first conductivity type is n and the second conductivity type is p.
Claim 11
Dependent Claim 125 words
A thin film transistor of a first conductivity type comprising: a thin film layer of semiconductive material, the thin film layer comprising a source region, a drain region, a drain offset region and a channel region; the source and drain regions being conductively doped with a conductivity enhancing impurity of the first conductivity type to a concentration effective to render such source and drain regions electrically conductive; the channel region being doped with a conductivity enhancing impurity to a first concentration; the drain offset region being doped with a conductivity enhancing impurity of a second conductivity type to a second concentration, the second concentration being less than the first concentration; a gate positioned operatively adjacent the channel region; and the drain offset not being gated.
Claim 12
Dependent Claim 125 words
A thin film transistor of a first conductivity type comprising: a thin film layer of semiconductive material, the thin film layer comprising a source region, a drain region, a drain offset region and a channel region; the source and drain regions being conductively doped with a conductivity enhancing impurity of the first conductivity type to a concentration effective to render such source and drain regions electrically conductive; the channel region being doped with a conductivity enhancing impurity to a first concentration; the drain offset region being doped with a conductivity enhancing impurity of a second conductivity type to a second concentration, the second concentration being less than the first concentration; a gate positioned operatively adjacent the channel region; and the drain offset not being gated.
Claim 13
Dependent Claim 88 words
A thin film transistor of a first conductivity type comprising: a thin film layer of semiconductive material, the thin film layer comprising a drain offset region and a channel region, the channel region being doped with a conductivity enhancing impurity to a first concentration; the drain offset region being doped with a conductivity enhancing impurity of a second conductivity type to a second concentration, the second concentration being less than the first concentration; a gate positioned operatively adjacent the channel region; and the drain offset not being gated.
Claim 14
Dependent Claim 88 words
A thin film transistor of a first conductivity type comprising: a thin film layer of semiconductive material, the thin film layer comprising a drain offset region and a channel region, the channel region being doped with a conductivity enhancing impurity to a first concentration; the drain offset region being doped with a conductivity enhancing impurity of a second conductivity type to a second concentration, the second concentration being less than the first concentration; a gate positioned operatively adjacent the channel region; and the drain offset not being gated.

References Cited (Backward Citations)

US4318216A Cited
US5021845A Cited
JPH03158775A Cited
US5124769A Cited
US5422505A Cited
US5396099A Cited
JPH04254335A Cited
US5104818A Cited
US5348897A Cited
US5434093A Cited
US5510278A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-08-18 2001-02-17 2001-08-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-08-18 2005-02-17 2005-08-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-08-18 2009-02-17 2009-08-19 $7700.00 Window Closed / Lapsed

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