US5657285A
Expired / Lapsed
US
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Pipelined address memories, and systems and methods using the same
Assignee: Intellectual Ventures II LLC
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Filing: 1996-06-14
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Granted: 1997-08-12
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Expires: 2016-06-14
Abstract
Abstract A method of operating a memory device including a plurality of memory banks, each bank having an array of memory cells and associated control circuitry in which an external row address strobe generated by an external device is received. The received row address strobe includes a logic high period and a logic low period. During the logic high period of the row address strobe, a first one of the memory banks is caused to enter an active cycle and simultaneously a second one of the memory banks is caused to enter a precharge cycle. During the logic low period of the row address strobe, the first memory bank is caused to enter a precharge cycle and simultaneously the second memory bank is caused to enter an active cycle.
Inventors
- 👤 G. R. Mohan Rao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:02
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/00; G11C7/10; G11C7/1015; G11C7/1042; G11C11/4076; G11C7/1039; G11C7/12; G11C7/22; G11C8/00; G11C8/18
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
122 words
A method of operating memory device including a plurality of memory banks, each bank having an array of memory cells and associated control circuitry, the method comprising the steps of: receiving an external row address strobe generated by an external device, said row address strobe including a logic high period and a logic low period; during the logic high period of the row address strobe, causing a first one of the memory banks to enter an active cycle and a second one of the memory banks to enter a precharge cycle; and during the logic low period of the row address strobe, causing the first memory bank to enter a precharge cycle and the second memory bank to enter an active cycle.
Claim 2
Independent Claim
122 words
A method of operating memory device including a plurality of memory banks, each bank having an array of memory cells and associated control circuitry, the method comprising the steps of: receiving an external row address strobe generated by an external device, said row address strobe including a logic high period and a logic low period; during the logic high period of the row address strobe, causing a first one of the memory banks to enter an active cycle and a second one of the memory banks to enter a precharge cycle; and during the logic low period of the row address strobe, causing the first memory bank to enter a precharge cycle and the second memory bank to enter an active cycle.
Claim 3
Dependent Claim
78 words
The method of claim 1 wherein said step of causing the first memory bank to enter an active cycle and the second memory bank to enter a precharge cycle comprises the substeps of: generating first and second internal row address strobes from the external row address strobe; initiating the active cycle of the first bank with the first internal row address strobe and initiating the precharge cycle of the second bank with the second internal row address strobe.
Claim 4
Dependent Claim
78 words
The method of claim 1 wherein said step of causing the second memory bank to enter an active cycle and the first memory bank to enter a precharge cycle comprises the substeps of: generating first and second internal row address strobes from the external row address strobe; initiating the active cycle of the second bank with the first internal row address strobe; and initiating the precharge cycle of the first bank with the second internal row address strobe.
Claim 5
Dependent Claim
156 words
A memory comprising: a first memory bank comprising an array of memory cells and associated access control circuitry including sense amplifiers, address decoding circuitry and precharge control circuitry; a second memory bank comprising an array of memory cells and associated access control circuitry including sense amplifiers, address decoding circuitry, and precharge control circuitry; at least one address bus for transferring row and column addresses to said access control circuitry of said respective first and second banks; a data bus for exchanging data with said first and second memory banks; and row clock generator circuitry for receiving a row address from an external source and generating in response internal row clocks, said internal row clocks timing active and precharge cycles of said first and second memory banks such that a selected one of said memory banks is in an active cycle and an other selected one of said memory banks is substantially simultaneously in a precharge cycle.
Claim 6
Dependent Claim
156 words
A memory comprising: a first memory bank comprising an array of memory cells and associated access control circuitry including sense amplifiers, address decoding circuitry and precharge control circuitry; a second memory bank comprising an array of memory cells and associated access control circuitry including sense amplifiers, address decoding circuitry, and precharge control circuitry; at least one address bus for transferring row and column addresses to said access control circuitry of said respective first and second banks; a data bus for exchanging data with said first and second memory banks; and row clock generator circuitry for receiving a row address from an external source and generating in response internal row clocks, said internal row clocks timing active and precharge cycles of said first and second memory banks such that a selected one of said memory banks is in an active cycle and an other selected one of said memory banks is substantially simultaneously in a precharge cycle.
Claim 7
Dependent Claim
31 words
The memory of claim 4 wherein said internal row clocks are further operable to time the transfer of row addresses to said memory banks via said at least one address bus.
Claim 8
Dependent Claim
43 words
The memory of claim 4 and further comprising column clock generation circuitry for receiving a column address strobe from an external source and generating in response internal column clocks for timing the precharge and active cycles of said first and second memory banks.
Claim 9
Dependent Claim
30 words
The memory of claim 6 wherein said column clocks are further operable to time the transfer of column addresses to said memory banks via said at least one address bus.
Claim 10
Dependent Claim
16 words
The memory of claim 4 wherein said arrays comprise arrays of dynamic random access memory cells.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-11 | 2001-02-10 | 2001-08-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-11 | 2005-02-10 | 2005-08-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-11 | 2009-02-10 | 2009-08-12 | $7700.00 | Window Closed / Lapsed |