EP0303811A1
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EP
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Pipelined memory chip
Assignee: International Business Machines Corp
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Filing: 1988-07-05
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Granted: —
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Expires: 2008-07-05
Abstract
Abstract A semiconductor random access memory chip wherein the cycle time is less than the access time for any combination of read or write sequence. The semiconductor random access memory chip is partitioned into relatively small sub-arrays with local decoding (RS, WS) and precharging (BLPC). The memory chip operates in a pipelined manner with more than one access propagating through the chip at any given time and wherein the cycle time is limited by sub-array cycles wherein the cycle time is less than the access time for a memory chip having cycle times greater than access times for accesses through the same sub-array. The memory chip also incorporates dynamic storage techniques for achieving very fast access and precharge times.
Inventors
- 👤 Barbara Alane Chappell
- 👤 Terry Ivan Chappell
- 👤 Stanley Everett Schuster
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 20:13
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/12; G11C7/00; G11C7/10; G11C7/1015; G11C7/1039; G11C7/12
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
70 words
Pipelined semiconductor 2 n Kbit memory chip, n being an integer not less than 2, said chip being segmented into a plurality of 2 n-y memory sub-arrays of 2 y Kbits arranged in columns and rows on said chip, characterized in that each one of said 2 n-y memory sub-arrays includes a separate associated word line driver circuit means, sense amplifier circuit means and independent precharge circuit means connected thereto.
Claim 2
Dependent Claim
70 words
Pipelined semiconductor 2 n Kbit memory chip, n being an integer not less than 2, said chip being segmented into a plurality of 2 n-y memory sub-arrays of 2 y Kbits arranged in columns and rows on said chip, characterized in that each one of said 2 n-y memory sub-arrays includes a separate associated word line driver circuit means, sense amplifier circuit means and independent precharge circuit means connected thereto.
Claim 3
Dependent Claim
61 words
Pipelined semiconductor 2 n Kbit memory chip according to claim 1, characterized by a plurality of word lines, a first group of said plurality of word lines disposed on a first metal layer and a second group of the plurality of word lines disposed on a second metal layer, and a plurality of bit lines disposed on the second metal layer.
Claim 4
Dependent Claim
52 words
Pipelined semiconductor 2 n Kbit memory chip according to claim 1, characterized in that each of said independent precharge circuit means of each of said segmented memory sub-arrays provides local self-timed reset and precharge function for each segmented memory array independent of said other of said plurality of 2 n-y memory arrays.
Claim 5
Dependent Claim
67 words
Pipelined semiconductor 2 n Kbit memory chip according to claim 3, characterized in that each of the segmented memory sub-arrays further includes a separate read bitswitch and read switch circuit means and a separate write bitswitch and write switch circuit means, and wherein a separate word line and bitswitch decoder/driver circuit means is connected to the said memory sub-arrays in each of said rows on said chip.
Claim 6
Dependent Claim
59 words
Pipelined semiconductor 2 n Kbit memory chip according to claim 3, characterized in that the memory chip exhibits an access time t for providing data from said memory chip and wherein said local reset and precharge circuits of each of said segmented memory sub-arrays provides a cycle time for each sub-array which is less than chip access time t.
Claim 7
Dependent Claim
46 words
Pipelined semiconductor 2 n Kbit memory chip according to claim 5, characterized in that the segmented memory sub-arrays including independent local decoding and precharging means operate in a pipelined manner with greater than one access propagating through said 2 n Kbit memory chip at one time.
Claim 8
Dependent Claim
53 words
Pipelined semiconductor 2 n Kbit memory chip according to claim 6, characterized by further including row and column address circuits disposed on said chip connected to said word line and bitswitch decoder/driver circuit means and responsive to input address access signals for selecting ones of said 2 n-y segmented memory sub-arrays for access.
Claim 9
Dependent Claim
25 words
Pipelined semiconductor 2 n Kbit memory chip according to claim 3, characterized by comparing circuits for determining said sub-arrays being accessed by separate access signals.
Claim 10
Dependent Claim
89 words
Pipelined semiconductor 2 n Kbit memory chip according to claim 3, characterized in that the memory chip exhibits an access time t, further including global blocks on said chip external to said sub-arrays each containing clock circuit means, address buffer means, row decoder means, data output bluffer means and word driver means associated with said plurality of sub-arrays, each of said global blocks including separate reset and precharge circuit means for providing a cycle time for each of said global blocks which is less than chip access time t.
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