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EP0145488A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1984-12-12
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Granted: —
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Expires: 2004-12-12
Abstract
Abstract A semiconductor memory device, such as a mask ROM device, wherein precharge time is controlled by the chargeup level of a dummy bit line. The semiconductor memory device comprises a gate circuit (4) for selecting a desired bit line, (BL, ...BL m ), a dummy bit line (DBL) having a chargeup characteristic equivalent to that of each of the bit lines, a dummy bit line chargeup circuit (8) for charging the dummy bit line, and a chargeup circuit (6) for charging up the selected bit line from the time the bit line is selected to the time the chargeup of the dummy bit line is finished, on the basis of the chargeup level of the dummy bit line, thereby enabling chargeup of the selected bit line for the necessary period without the intervention of excess time.
Inventors
- 👤 Masanori Nagasawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 00:55
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C7/00; G11C7/12; G11C7/14
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
91 words
A semiconductor memory device comprising: a plurality of bit lines; a gate circuit for selecting a desired bit line; a dummy bit line having the chargeup characteristic equivalent to that of each of said bit lines; a dummy bit line chargeup circuit for charging said dummy bit line; and a chargeup circuit for charging up the selected bit line from the time said bit line is selected to the time the chargeup of said dummy bit line is finished on the basis of the chargeup level of said dummy bit line.
Claim 2
Dependent Claim
91 words
A semiconductor memory device comprising: a plurality of bit lines; a gate circuit for selecting a desired bit line; a dummy bit line having the chargeup characteristic equivalent to that of each of said bit lines; a dummy bit line chargeup circuit for charging said dummy bit line; and a chargeup circuit for charging up the selected bit line from the time said bit line is selected to the time the chargeup of said dummy bit line is finished on the basis of the chargeup level of said dummy bit line.
Claim 3
Dependent Claim
46 words
A semiconductor memory device according to claim 1, wherein said semiconductor memory device comprises a clock generating circuit for generating a clock signal which becomes active from the time said bit line is selected to the time the chargeup of said dummy bit line is finished.
Claim 4
Dependent Claim
57 words
A semiconductor memory device according to claim 2, wherein said clock generating circuit comprises a first gate circuit for generating a signal indicating that any bit line is selected and a second gate circuit generates said clock signal based on said signal output from said first gate circuit and the potential level of said dummy bit line.
Claim 5
Dependent Claim
37 words
A semiconductor memory device according to claim 3, wherein said first gate circuit is a NOR gate circuit and said second gate circuit includes a second NOR gate and an inverter connected to said second NOR gate.
Claim 6
Dependent Claim
77 words
A semiconductor memory device according to claim 1, wherein said dummy bit line chargeup circuit comprises a series connection of first and second transistors connected between first and second power terminals of a power source, the common connection point of said first and second transistors being connected to said dummy bit line, said first transistor being turned on after the time said bit line is selected, and said second transistor being controlled by a chip enable signal.
Claim 7
Dependent Claim
41 words
A semiconductor memory device according to claim 5, wherein said common connection point is connected to said dummy bit line via a dummy transistor having the transfer characteristic equivalent to that of said gate circuit for selecting a desired bit line.
Claim 8
Dependent Claim
36 words
A semiconductor memory device according to claim 5, or 6, wherein said dummy bit line chargeup circuit further comprises a third transistor connected in parallel to said first transistor and controlled by said chip enable signal.
Claim 9
Dependent Claim
79 words
A semiconductor memory device according to claim 2, wherein said chargeup circuit comprises a series connection of first and second transistors connected between first and second power terminals of a power source, the common connection point of said first and second transistors being connected to the output terminal of said gate circuit for selecting a desired bit line, said first transistor being turned on by said clock signal, and said second transistor being controlled by a chip enable signal.
Claim 10
Dependent Claim
31 words
A semiconductor memory device according to claim 8, wherein said chargeup circuit further comprises a third transistor connected in parallel to said first transistor and controlled by said chip enable signal.
Claim 11
Dependent Claim
39 words
A semiconductor memory device according to any preceding claim,wherein said gate circuit for selecting a desired bit line comprises a plurality of transfer gate transistors each connected between a bit line and an output terminal of said gate circuit.
Claim 12
Dependent Claim
69 words
A semiconductor memory device according to any preceding claim, wherein said gate circuit for selecting a desired bit line comprises a plurality of first groups of transfer gate transistors each group selecting a bit line among a group of bit lines, and a second group of transfer gate transistors for selecting a bit line among a plurality of bit lines selected by said first groups of transfer gate transistors.
Claim 13
Dependent Claim
38 words
A semiconductor memory device according to any preceding claim, wherein a plurality of memory cells are connected to each of said bit lines, and the same number of dummy memory cells are connected to said dummy bit line.
Claim 14
Dependent Claim
39 words
A semiconductor memory device according to claim 12, wherein said memory cells and said dummy memory cells are comprised of MOS transistors, and said MOS transistors of said dummy memory cells are always kept in a turned off condition.
Claim 15
Dependent Claim
38 words
A semiconductor memory device according to claim 13, wherein the thickness of the gate insulation film of each of said MOS transistors of said memory cells is changed in accordance with the data stored in said memory cell.
Claim 16
Dependent Claim
38 words
A semiconductor memory device according to claim 13, wherein the impurity concentration of the channel region of each of said MOS transistors of said memory cells is changed in accordance with the data stored in said memory cell.
Claim 17
Dependent Claim
90 words
A semiconductor memory device comprising : a bit line ; a gate circuit for selecting the bit line ; a dummy bit line having a chargeup characteristic equivalent to said bit line ; circuit a dummy bit line chargeup circuit for charging said dummy bit line ; and a chargeup circuit for charging up the selected bit line from a time said bit line is selected to a time the chargeup of said dummy bit line is finished on the basis of the chargeup level of said dummy bit line.
Claim 18
Dependent Claim
90 words
A semiconductor memory device comprising : a bit line ; a gate circuit for selecting the bit line ; a dummy bit line having a chargeup characteristic equivalent to said bit line ; circuit a dummy bit line chargeup circuit for charging said dummy bit line ; and a chargeup circuit for charging up the selected bit line from a time said bit line is selected to a time the chargeup of said dummy bit line is finished on the basis of the chargeup level of said dummy bit line.
Claim 19
Dependent Claim
34 words
A semiconductor memory device as claimed in claim 16, comprising a plurality of bit lines, including said bit line, all having similar chargeup characteristics similar to the chargeup characteristic of the dummy bit line.
Claim 20
Dependent Claim
37 words
A semiconductor memory device as claimed in claim 17, wherein said dummy bit line has a chargeup characteristic equivalent to the chargeup characteristic of that one of said plurality of bit lines having the slowest rising characteristic.
References Cited (Backward Citations)
No citation records indexed.
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