EP0591009A2
Expired / Lapsed
EP
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Semiconductor memory
Assignee: Samsung Electronics Co Ltd
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Filing: 1993-10-01
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Granted: —
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Expires: 2013-10-01
Abstract
Abstract A synchronous dynamic random access memory is capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock CLK and includes a plurality of memory banks 12, 14 each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit (70, 108) for receiving a row address strobe signal RAS ¯ and latching a logic level of the row address strobe signal RAS ¯ in response to the clock CLK, an address input circuit for receiving an externally generated address SRA10, SRA11 selecting one of the memory banks, and a circuit (540, 542) for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank 12, 14 selected by the address, and inactivation signals to unselected memory banks 12, 14 when the latched logic level is a first logic level, so that the selected memory bank 12, 14 responsive to the activation signal operates in the active cycle while the unselected memory banks (12, 14) responsive to the inactivation signals operate in the precharge cycle.
Inventors
- 👤 Churoo Park
- 👤 Hyun-Soon Jang
- 👤 Chull-Soo Kim
- 👤 Myung-Ho Kim
- 👤 Seung-Hun Lee
- 👤 Si-Yeol Lee
- 👤 Ho-Cheol Lee
- 👤 Tae-Jin Kim
- 👤 Yun-Ho Choi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 05:22
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/1018; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/40618; G11C11/4063; G11C11/407; G11C11/4076; G11C11/408; G11C11/4082; G11C11/4087; G11C7/1045; G11C7/1072; G11C7/22; G11C7/222; G11C7/225; G11C2207/00; G11C2207/22; G11C2207/2281
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
92 words
In a semiconductor memory formed on a semiconductor chip having various operation modes, the combination of: address input means for receiving an external address (RA0∼RA6) designating at least one of the operation modes of the chip; means (200) for generating a mode set control signal (φ MRS ) in a mode set operation; and means (202) for storing codes (MDST0∼MDST6) based on the external address in response to the mode set control signal and producing an operation mode signal (SZn, CLj, φ INTEL ) representing the operation mode determined by the codes.
Claim 2
Dependent Claim
80 words
A semiconductor memory having a plurality of internal operation modes and comprising: means (203) for producing a power-on signal (φ VCCH ) upon a power supply potential reaching a predetermined value after the application of power; and means (202) for automatically storing a plurality of code signals (MDST0∼MDST6) in response to the power-on signal and producing internal operation mode signals (SZn, CLj, φ INTEL ) indicating selected ones of the internal operation modes which are defined by the code signals.
Claim 3
Dependent Claim
175 words
A dynamic random access memory comprising: a plurality of memory banks (12, 14), each bank including a plurality of memory cells and operable in either an active cycle indicating a read cycle or a write cycle, or a precharge cycle; first means (70, 108) for receiving a row address strobe signal ( RAS ¯ ) and producing a first signal (φ RP ); second means (338) for receiving a column address strobe signal ( CAS ¯ ) and producing a second signal (φ C ); third means (340) for receiving a write enable signal ( WE ¯ ) and producing a third signal (φ WRC ); address input means for receiving addresses (SRA10, SRA11, SRA11 ¯ ) indicating the selection of the memory banks; and logic means (114) responsive to the first, second and third signals and the address signals including latch means (154, 156) corresponding to the respective banks for storing data representing the active cycle for one of the banks selected by the address and data representing the precharge cycle for unselected banks.
Claim 4
Dependent Claim
196 words
A dynamic random access memory receiving an external clock (φ CLK ) and comprising: a plurality of memory banks (12, 14) each including a plurality of memory cells and operable in either an active cycle indicating a read cycle or a write cycle, or a precharge cycle; means (70, 108, 550) for receiving a row address strobe signal ( RAS ¯ ) and latching a logic level of the row address strobe signal in response to one of a rising edge and a falling edge of the clock; address input means for receiving an externally generated address (SRA11, SRA11 ¯ ) selecting one of the memory banks; and means (540, 542) for receiving the latched logic level from the receiving and latching means and the address from the address input means, and for outputting an activation signal (φRC1, φRC2)to the memory bank selected by the address and inactivation signals (φRC1, φRC2) to unselected memory banks when the latched logic level is at a first logic level, whereby the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.
Claim 5
Dependent Claim
78 words
A semiconductor memory formed on a semiconductor chip receiving an external clock (CLK) to the chip and outputting data read out from memory cells via data output buffer means (284), said memory comprising: means (350, 352, 530) for generating a burst length signal (φ TRST ) representing a time interval of output of data and outputting data in synchronism with the clock via the data output buffer means during the time interval corresponding to the burst length signal.
Claim 6
Dependent Claim
296 words
A semiconductor memory comprising: a memory cell array (16T) having a plurality of memory cells (30) arranged in rows and columns; a plurality of sub-arrays (22) provided by partitioning the memory cell array in the row direction, each of the sub-arrays having a plurality of word lines (WL0∼WL255) respectively connected to associated columns of the memory cells and a plurality of bit lines (28) respectively connected to associated rows of the memory cells, the bit lines of each sub-array divided into first groups (28L1∼28L256) of bit lines and second groups (28R1∼28R256) of bit lines, the respective ones of which are divided into first sub-groups (28L1, 28L3, ..., 28L255; 28R1, 28R3, ..., 28R255) of bit lines and second sub-groups (28L2, 28L4, ..., 28L256; 28R2, 28R4, 28R256) of bit lines, the first groups of each sub-array alternately arranged with the second groups thereof, the first sub-groups of each sub-array alternately arranged with the second sub-groups thereof; and I/O buses (26) respectively disposed in parallel to the word lines between the sub-arrays and on outer sides of the sub-arrays, and divided into first I/O buses and second I/O buses respectively arranged at odd and even positions, each I/O bus divided into first I/O lines (I/O0, I/O0 ¯ ;I/O1, I/O1 ¯ ) and second I/O lines (I/O2, I/O2 ¯ ; I/O3, I/O3 ¯ ), the first and the second I/O lines of the respective first I/O buses respectively connected via column selection switches with the bit lines of the first and the second subgroups of the first groups of sub-arrays adjacent thereto, the first and the second I/O lines of the respective second I/O buses respectively connected via column selection switches with the bit lines of the first and the second subgroups of the second groups of sub-arrays adjacent thereto.
Claim 7
Dependent Claim
15 words
A memory according to two or more of claims 1 to 6, in any combination.
Claim 8
Dependent Claim
47 words
A semiconductor memory device having a plurality of operating modes and comprising first means for receiving an input signal representing a selected one of said modes and second means for setting the operating mode of the memory in accordance with the mode represented by said input signal.
Claim 9
Dependent Claim
30 words
A memory according to any of the preceding claims, further comprising any one or more of the features disclosed in the accompanying specification, claims, abstract and/or drawings, in any combination.
References Cited (Backward Citations)
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