EP0145320A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method for multiplexing a memory data bus
Assignee: Motorola Solutions Inc
•
Filing: 1984-11-14
•
Granted: —
•
Expires: 2004-11-14
Abstract
Abstract @ The amount of data obtained from parallel connected memories is increased by using the column precharge time of one of the memories to access data from another one of the memory devices. By having the memory devices connected in parallel they each receive the same address and the same row address strobe. The column address of one of the first memories is then strobed in by the column address strobe signal and data is accessed from this first memory. Then while the first memory's columns are being precharged the column address strobe signal is activated for a second memory and data is obtained from the second memory. The procedure can be repeated so that after the second memory's data is retrieved the second column address strobe signal is inactivated so that the columns of the second memory can be precharged at the same time a new column address is strobed into the first memory. Thus, memory bandwidth is increased without the need to widen the memory data bus.
Inventors
- 👤 Jay W. Gustin
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 13:28
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/14; G06F3/153; G11; G11C; G11C7/00; G09; G09G; G09G1/00; G11C7/22
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
53 words
A method for increasing the amount of data accessed from a first and a second bank of memories within a given period of time comprising: accessing data from the first memory bank; precharging the first memory bank; and accessing data from the second memory bank during the precharging of the first memory bank.
Claim 2
Independent Claim
53 words
A method for increasing the amount of data accessed from a first and a second bank of memories within a given period of time comprising: accessing data from the first memory bank; precharging the first memory bank; and accessing data from the second memory bank during the precharging of the first memory bank.
Claim 3
Dependent Claim
41 words
The method of claim 1 further including placing the accessed data from both memory banks on the same bus so that the accessed data is equivalent to a byte twice as long as a byte from a single bank of memories.
Claim 4
Independent Claim
87 words
A method of increasing bandwidth of at least a first and a second memory which are connected to receive a plurality of common signals from an input/output device except for a column address strobe (CAS) which each memory receives separately, the method comprising: strobing in column addresses for the first memory; strobing in column addresses for the second memory after data addressed in the first memory is read; and precharging the first memory during the time that the column addresses are being strobed into the second memory.
Claim 5
Independent Claim
87 words
A method of increasing bandwidth of at least a first and a second memory which are connected to receive a plurality of common signals from an input/output device except for a column address strobe (CAS) which each memory receives separately, the method comprising: strobing in column addresses for the first memory; strobing in column addresses for the second memory after data addressed in the first memory is read; and precharging the first memory during the time that the column addresses are being strobed into the second memory.
Claim 6
Independent Claim
141 words
A method for increasing memory bandwidth for two memory banks connected in parallel and having a common row address strobe and separate column address strobes, comprising: activating the column address strobe for a first of the two memories; activating the column address strobe for the second of the two memories upon completion of the activation of the column address strobe for the first memory; precharging the first memory during activation of the column address strobe for the second memory; reactivating the column address strobe for the first memory upon completion of the activation of the column address strobe of the second memory; precharging the second memory during reactivation of the column address strobe for the first memory; and reactivating the column address strobe of the second memory upon completion of the reactivation of the column address strobe for the first memory.
Claim 7
Independent Claim
141 words
A method for increasing memory bandwidth for two memory banks connected in parallel and having a common row address strobe and separate column address strobes, comprising: activating the column address strobe for a first of the two memories; activating the column address strobe for the second of the two memories upon completion of the activation of the column address strobe for the first memory; precharging the first memory during activation of the column address strobe for the second memory; reactivating the column address strobe for the first memory upon completion of the activation of the column address strobe of the second memory; precharging the second memory during reactivation of the column address strobe for the first memory; and reactivating the column address strobe of the second memory upon completion of the reactivation of the column address strobe for the first memory.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.