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US5656953A Expired / Lapsed US ⏱️ 0.0 years remaining

Low overhead memory designs for IC terminals

Assignee: Texas Instruments Inc
•
Filing: 1996-03-26
•
Granted: 1997-08-12
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Expires: 2016-03-26
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Abstract

Abstract An integrated circuit includes a terminal which is accessible externally of the integrated circuit, and circuitry (LOB) coupled to said terminal and operable to latch at said terminal a signal applied to said terminal by a source (ICT) external to said integrated circuit.

Inventors

  • 👤 Lee D. Whetsel

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 21:11
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541; G01R31/31712; G01R31/31715; G01R31/318572; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/2733

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 142 words
An electronic system, comprising: an integrated circuit having an output terminal which is physically accessible externally thereof, and having an output buffer coupled to said output terminal for driving said output terminal to a plurality of logic levels; a source physically external to said integrated circuit and connected to said output terminal of said integrated circuit for driving said output terminal to said plurality of logic levels; and said integrated circuit including circuitry which is coupled to said output terminal and which is operable, when said physically external source and said output buffer concurrently attempt to drive said output terminal to different ones of said plurality of logic levels, to permit said physically external source to drive said output terminal without contention from said output buffer regardless of which of said plurality of logic levels said output buffer is attempting to drive.
Claim 2
Dependent Claim 142 words
An electronic system, comprising: an integrated circuit having an output terminal which is physically accessible externally thereof, and having an output buffer coupled to said output terminal for driving said output terminal to a plurality of logic levels; a source physically external to said integrated circuit and connected to said output terminal of said integrated circuit for driving said output terminal to said plurality of logic levels; and said integrated circuit including circuitry which is coupled to said output terminal and which is operable, when said physically external source and said output buffer concurrently attempt to drive said output terminal to different ones of said plurality of logic levels, to permit said physically external source to drive said output terminal without contention from said output buffer regardless of which of said plurality of logic levels said output buffer is attempting to drive.
Claim 3
Dependent Claim 13 words
The system of claim 1, wherein said external source is a testing apparatus.
Claim 4
Independent Claim 126 words
A method of operating an electronic system wherein an output terminal of an integrated circuit is physically accessible externally of the integrated circuit and is connected to a source physically external to the integrated circuit, comprising the steps of: attempting to drive the output terminal to one of a plurality of logic levels using an output buffer of the integrated circuit while concurrently attempting to drive the output terminal to another of the plurality of logic levels using the physically external source, said another logic level differing from said one logic level; and thereafter permitting the physically external source to drive the output terminal without contention from the output buffer regardless of which of said plurality of logic levels the output buffer is attempting to drive.
Claim 5
Independent Claim 126 words
A method of operating an electronic system wherein an output terminal of an integrated circuit is physically accessible externally of the integrated circuit and is connected to a source physically external to the integrated circuit, comprising the steps of: attempting to drive the output terminal to one of a plurality of logic levels using an output buffer of the integrated circuit while concurrently attempting to drive the output terminal to another of the plurality of logic levels using the physically external source, said another logic level differing from said one logic level; and thereafter permitting the physically external source to drive the output terminal without contention from the output buffer regardless of which of said plurality of logic levels the output buffer is attempting to drive.
Claim 6
Dependent Claim 15 words
The method of claim 3, wherein said another logic level is a test logic level.

References Cited (Backward Citations)

US3739193A Cited
GB2220272A Cited
US5134314A Cited
EP0518550A2 Cited
EP0522413A2 Cited
US5526310A Cited
EP0604032B1 Cited
US5469473A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-08-11 2001-02-10 2001-08-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-08-11 2005-02-10 2005-08-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-08-11 2009-02-10 2009-08-12 $7700.00 Window Closed / Lapsed

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