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Patent US5656528A successfully refreshed from Google Patents.
US5656528A
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Method of forming a dynamic random access memory
Assignee: Altera Corp
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Filing: 1994-12-12
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Granted: 1997-08-12
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Expires: 2014-12-12
Abstract
Abstract A dynamic random access memory. The memory includes a write transistor N3 and a read transistor N2. In a preferred embodiment the write transistor has a threshold level higher than the read transistor. A sense amplifier senses and amplifies a difference in voltage between a bit line and a sense node that is developed when the read transistor permits or does-not permit current to flow between ground an a bit line. Associated semiconductor device structures and fabrication techniques are also disclosed.
Inventors
- 👤 Sven E. Wahlstrom
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:19
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405; G11C11/4063; G11C11/407; G11C11/4074; G11C11/409; G11C11/4091; G11C11/4096; G11C11/4099
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
181 words
In the fabrication of multilevel semiconductor integrated circuits, a method of forming a dynamic random access memory cell in multilayers of silicon semiconductor material comprising the steps of: providing a first silicon substrate; forming a storage capacitor on said first substrate for said memory cell; forming a first dielectric layer on a surface of said first substrate and said capacitor; providing a second silicon substrate; forming a first silicon epitaxial layer on one surface of said second silicon substrate and a second dielectric layer on a surface of said first epitaxial layer; stacking said second substrate on said first substrate, with first and second silicon dielectric layers in contact; fusing said dielectric layers together, forming a dielectric fusion interface; removing said second substrate by etching thereby leaving said first substrate as support for first epitaxial layer; forming at least two electrical components in said first epitaxial layer, including at least one transistor; and coupling said storage capacitor to said at least one transistor to form a dynamic random access memory cell, said storage capacitor formed below a gate of said transistor.
Claim 2
Dependent Claim
181 words
In the fabrication of multilevel semiconductor integrated circuits, a method of forming a dynamic random access memory cell in multilayers of silicon semiconductor material comprising the steps of: providing a first silicon substrate; forming a storage capacitor on said first substrate for said memory cell; forming a first dielectric layer on a surface of said first substrate and said capacitor; providing a second silicon substrate; forming a first silicon epitaxial layer on one surface of said second silicon substrate and a second dielectric layer on a surface of said first epitaxial layer; stacking said second substrate on said first substrate, with first and second silicon dielectric layers in contact; fusing said dielectric layers together, forming a dielectric fusion interface; removing said second substrate by etching thereby leaving said first substrate as support for first epitaxial layer; forming at least two electrical components in said first epitaxial layer, including at least one transistor; and coupling said storage capacitor to said at least one transistor to form a dynamic random access memory cell, said storage capacitor formed below a gate of said transistor.
Claim 3
Dependent Claim
51 words
The method of forming a dynamic random access memory cell as recited in claim 1 further comprising the step of forming a transistor in said first silicon substrate, coupled to said storage capacitor and coupled to said electrical component in first epitaxial layer to form a dynamic random access memory cell.
Claim 4
Dependent Claim
110 words
The method of forming a dynamic random access memory cell as recited in claim 1 wherein the electrical components formed in said first epitaxial layer comprise a first, write transistor coupled at its source or drain to a first plate of said storage capacitor in said first substrate and a bit line, and a second, read transistor having a first terminal thereof coupled to a first terminal of a third transistor and a second terminal coupled to a bit line, said third transistor comprising a gate coupled to said first plate of said storage capacitor, a word line forming a gate of both said read transistor and said write transistor.
Claim 5
Dependent Claim
23 words
The method of forming a dynamic random access memory cell as recited in claim 1 wherein said capacitor formed is a trench capacitor.
Claim 6
Dependent Claim
41 words
The method of forming a dynamic random access memory cell as recited in claim 1 wherein said capacitor formed is a capacitor, having a polysilicon gate terminal and a diffusion region terminal at a fixed potential in the first silicon substrate.
Claim 7
Dependent Claim
103 words
The method of forming a dynamic random access memory cell as recited in claim 1, wherein said capacitor comprises: a first plate comprising a polysilicon gate layer, above an oxide layer on said surface of said first silicon substrate, and beneath said dielectric fusion interface; a second plate, below said first plate, in said first silicon substrate at a fixed potential, wherein said oxide layer is a first dielectric material for said capacitor; and a third plate, above said first plate, in said first epitaxial layer at said fixed potential, wherein said dielectric fusion interface is a second dielectric material for said capacitor.
Claim 8
Dependent Claim
53 words
The method of forming a dynamic random access memory cell as recited in claim 6, wherein said second plate comprises: an inversion layer in a gate area in said first silicon substrate between grounded diffusion regions and beneath said oxide and polysilicon gate; and said grounded diffusion regions in the first silicon substrate.
References Cited (Backward Citations)
US3593037A
Cited
US3876991A
Cited
EP0175378A2
Cited
US4829018A
Cited
US5127739A
Cited
US5424235A
Cited
US5302542A
Cited
US5418177A
Cited
US5438009A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-11 | 2001-02-10 | 2001-08-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-11 | 2005-02-10 | 2005-08-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-11 | 2009-02-10 | 2009-08-12 | $7700.00 | Window Closed / Lapsed |