Method and system for storing information in a processing system

Claim 2

A processing system, comprising: a register for storing information; at least one execution unit for processing said information in response to an instruction specifying said register; N buffers coupled to said execution unit for storing said information, wherein N is a integer number greater than one; and N control units coupled to said execution unit, said N control units being cascadably connected to one another and respectively associated with said N buffers, and each for selectively allocating only its respectively associated buffer to store said information in response to said instruction.

Claim 3

The system of claim 1 wherein each said control unit indicates to said execution unit whether said information is to be read from its respectively associated buffer.

Claim 4

The system of claim 1 wherein each said control unit indicates to said execution unit whether said information is to be stored in its respectively associated buffer.

Claim 5

The system of claim 1 wherein said instruction follows an additional instruction in a programmed sequence.

Claim 6

The system of claim 4 wherein said additional instruction specifies said register.

Claim 7

The system of claim 5 wherein said instruction and said additional instruction specify said register as a destination register.

Claim 8

The system of claim 6 wherein a first control unit allocates its respectively associated buffer to store said information in response to said instruction, and a second control unit allocates its respectively associated buffer to store said information in response to said additional instruction, such that said control units indicate which of said buffers is most recently allocated to store said information.

Claim 9

The system of claim 7 wherein said instruction is dispatched to said execution unit no later than dispatch of said additional instruction, such that said first control unit indicates its respectively associated buffer is most recently allocated to store said information.

Claim 10

The system of claim 5 wherein said instruction specifies said register as a source register, and said additional instruction specifies said register as a destination register.

Claim 11

The system of claim 9 wherein a particular control unit allocates its respectively associated buffer to store said information in response to said additional instruction, such that said particular control unit indicates to said execution unit to read said information from its respectively associated buffer.

Claim 12

The system of claim 10 wherein said instruction is dispatched to said execution unit no later than dispatch of said additional instruction.

Claim 15

The method of claim 12 and further comprising the step of indicating, with each said control unit, to said execution unit whether said information is to be read from its respectively associated buffer.

Claim 16

The method of claim 12 and further comprising the step of indicating, with each said control unit, to said execution unit whether said information is to be stored in its respectively associated buffer.

Claim 17

The method of claim 12 wherein said processing step comprises the step of processing said information in response to said instruction, said instruction following an additional instruction in a programmed sequence, and said instruction and said additional instruction specifying said register as a destination register.

Claim 18

The method of claim 15 wherein said selectively allocating step comprises the steps of: allocating, with a first control unit, its respectively associated buffer to store said information in response to said instruction; and allocating, with a second control unit, its respectively associated buffer to store said information in response to said additional instruction, such that said control units indicate which of said buffers is most recently allocated to store said information.

Claim 19

The method of claim 16 and further comprising the step of dispatching said instruction to said execution unit no later than dispatch of said additional instruction, such that said first control unit indicates its respectively associated buffer is most recently allocated to store said information.

Claim 20

The method of claim 15 wherein said processing step comprises the step of processing said information in response to said instruction, said instruction following an additional instruction in a programmed sequence, said instruction specifying said register as a source register, and said additional instruction specifying said register as a destination register.

Claim 21

The method of claim 18 wherein said selectively allocating step comprises the step of allocating, with a particular control unit, its respectively associated buffer to store said information in response to said additional instruction, such that said particular control unit indicates to said execution unit to read said information from its respectively associated buffer.

Claim 22

The method of claim 19 and further comprising the step of dispatching said instruction to said execution unit no later than dispatch of said additional instruction.

Claim 23

A processing system, comprising: a register for storing information; at least one execution unit for processing said information in response to first and second instructions specifying said register as a destination register; first and second buffers coupled to said execution unit for storing said information; a first control unit coupled to said execution unit and to said first buffer for selectively allocating only said first buffer to store said information in response to said first instruction; and a second control unit coupled to said execution unit and to said second buffer for selectively allocating only said second buffer to store said information in response to said second instruction, such that said first and second control units indicate which of said first and second buffers is most recently allocated to store said information.

Claim 24

A processing system, comprising: a register for storing information; at least one execution unit for processing said information in response to first and second instructions specifying said register as a destination register; first and second buffers coupled to said execution unit for storing said information; a first control unit coupled to said execution unit and to said first buffer for selectively allocating only said first buffer to store said information in response to said first instruction; and a second control unit coupled to said execution unit and to said second buffer for selectively allocating only said second buffer to store said information in response to said second instruction, such that said first and second control units indicate which of said first and second buffers is most recently allocated to store said information.

Claim 25

The system of claim 21 wherein said first instruction follows said second instruction in a programmed sequence, and said first instruction is dispatched to said execution unit no later than dispatch of said second instruction, such that said first control unit indicates said first buffer is most recently allocated to store said information.

Claim 28

The method of claim 23 and further comprising the step of dispatching said first instruction to said execution unit no later than dispatch of said second instruction, such that said first control unit indicates said first buffer is most recently allocated to store said information, said first instruction following said second instruction in a programmed sequence.