US5491829A
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Method and system for indexing the assignment of intermediate storage buffers in a superscalar processor system
Assignee: International Business Machines Corp
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Filing: 1995-05-11
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Granted: 1996-02-13
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Expires: 2015-05-11
Abstract
Abstract A method and system for enhanced instruction dispatch efficiency in a superscalar processor system having a plurality of intermediate storage buffers, a plurality of general purpose registers, and a storage buffer index. Multiple scalar instructions may be simultaneously dispatched from a dispatch buffer to a plurality of execution units. Each of the multiple scalar instructions generally include at least one source operand and one destination operand. A particular one of the plurality of intermediate storage buffers is assigned to a destination operand within a selected one of the multiple scalar instructions. A relationship between the particular one of the plurality of intermediate storage buffers and a designated one of the plurality of general purpose registers is stored in the storage buffer index at that time when the instruction which has been dispatched is replaced in the dispatcher by another instruction in the application program sequence. Results of execution from the selected one of the multiple scalar instructions are stored in the particular one of the intermediate storage buffers when the selected instruction is executed. The storage buffer index is used to determine which storage buffers to use as source operands for those instructions which are dispatched between the time that a storage buffer has been assigned for a specific general purpose register and the results of execution are moved from the storage buffer into the general purpose register.
Inventors
- 👤 Chin-Cheng Kau
- 👤 Aubrey D. Ogden
- 👤 Donald E. Waldecker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 19:35
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3838; G06F9/384
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
225 words
A method for enhanced instruction dispatch efficiency in a superscalar processor system capable of simultaneously dispatching multiple scalar instructions from a dispatch buffer to a plurality of execution units during a single cycle, each of said multiple scalar instructions including at least one source operand and one destination operand, wherein results of execution of said multiple scalar instructions are stored in a plurality of general purpose registers, said method comprising the steps of: assigning a particular one of a plurality of intermediate storage buffers to a destination operand within each one of said multiple scalar instructions; storing a relationship between each one of said plurality of intermediate storage buffers and a designated one of said plurality of general purpose registers in a storage buffer index; temporarily storing results of execution of each one of said multiple scalar instructions in an assigned one of said plurality of intermediate storage buffers; and transferring said results of execution from a particular one of said plurality of intermediate storage buffers to an alternate one of said plurality of execution units for utilization in execution of an alternate one of said multiple scalar instructions utilizing said storage buffer index prior to a transfer of said results of execution from said particular one of said plurality of intermediate storage buffers to said designated one of said plurality of general purpose registers.
Claim 2
Independent Claim
225 words
A method for enhanced instruction dispatch efficiency in a superscalar processor system capable of simultaneously dispatching multiple scalar instructions from a dispatch buffer to a plurality of execution units during a single cycle, each of said multiple scalar instructions including at least one source operand and one destination operand, wherein results of execution of said multiple scalar instructions are stored in a plurality of general purpose registers, said method comprising the steps of: assigning a particular one of a plurality of intermediate storage buffers to a destination operand within each one of said multiple scalar instructions; storing a relationship between each one of said plurality of intermediate storage buffers and a designated one of said plurality of general purpose registers in a storage buffer index; temporarily storing results of execution of each one of said multiple scalar instructions in an assigned one of said plurality of intermediate storage buffers; and transferring said results of execution from a particular one of said plurality of intermediate storage buffers to an alternate one of said plurality of execution units for utilization in execution of an alternate one of said multiple scalar instructions utilizing said storage buffer index prior to a transfer of said results of execution from said particular one of said plurality of intermediate storage buffers to said designated one of said plurality of general purpose registers.
Claim 3
Dependent Claim
99 words
The method for enhanced instruction dispatch efficiency in a superscalar processor system of claim 1, wherein said step of storing a relationship between each one of said plurality of intermediate storage buffers and a designated one of a plurality of general purpose registers in a storage buffer index comprises storing an identifier for each one of said plurality of intermediate storage buffers in said storage buffer index, and accessing said identifier for each one of said plurality of intermediate storage buffers from said storage buffer index utilizing an identifier for each one of a plurality of general purpose registers.
Claim 4
Dependent Claim
100 words
The method for enhanced instruction dispatch efficiency in a superscalar processor system of claim 1, wherein said step of storing a relationship between each one of said plurality of intermediate storage buffers and a designated one of a plurality of general purpose registers in a storage buffer index comprises storing an identifier for said designated one of said plurality of general purpose registers in said storage buffer index, and accessing said identifier for said designated one of said plurality of general purpose registers from said storage buffer index-utilizing an identifier for each one of said plurality of intermediate storage buffers.
Claim 5
Independent Claim
230 words
A system for enhanced instruction dispatch efficiency in a superscalar processor system capable of simultaneously dispatching multiple scalar instructions from a dispatch buffer to a plurality of execution units during a single cycle, each of said multiple scalar instructions including at least one source operand and one destination operand, wherein results of execution of said multiple scalar instructions are stored in a plurality of general purpose registers, said system comprising: means for assigning a particular one of a plurality of intermediate storage buffers to a destination operand within each one of said multiple scalar instructions; means for storing a relationship between each one of said plurality of intermediate storage buffers and a designated one of said plurality of general purpose registers in a storage buffer index; means for temporarily storing results of execution of each one of said multiple scalar instructions in an assigned one of said plurality of intermediate storage buffers; and means for transferring said results of execution from a particular one of said plurality of intermediate storage buffers to an alternate one of said plurality of execution units for utilization in execution of an alternate one of said multiple scalar instructions utilizing said storage buffer index prior to a transfer of said results of execution from said particular one of said plurality of intermediate storage buffers to said designated one of said plurality of general purpose registers.
Claim 6
Independent Claim
230 words
A system for enhanced instruction dispatch efficiency in a superscalar processor system capable of simultaneously dispatching multiple scalar instructions from a dispatch buffer to a plurality of execution units during a single cycle, each of said multiple scalar instructions including at least one source operand and one destination operand, wherein results of execution of said multiple scalar instructions are stored in a plurality of general purpose registers, said system comprising: means for assigning a particular one of a plurality of intermediate storage buffers to a destination operand within each one of said multiple scalar instructions; means for storing a relationship between each one of said plurality of intermediate storage buffers and a designated one of said plurality of general purpose registers in a storage buffer index; means for temporarily storing results of execution of each one of said multiple scalar instructions in an assigned one of said plurality of intermediate storage buffers; and means for transferring said results of execution from a particular one of said plurality of intermediate storage buffers to an alternate one of said plurality of execution units for utilization in execution of an alternate one of said multiple scalar instructions utilizing said storage buffer index prior to a transfer of said results of execution from said particular one of said plurality of intermediate storage buffers to said designated one of said plurality of general purpose registers.
Claim 7
Dependent Claim
104 words
The system for enhanced instruction dispatch efficiency in a superscalar processor system of claim 4, wherein said means for storing a relationship between each one of said plurality of intermediate storage buffers and a designated one of a plurality of general purpose registers in a storage buffer index comprises means for storing an identifier for each one of said plurality of intermediate storage buffers in said storage buffer index, and means for accessing said identifier for each one of said plurality of intermediate storage buffers from said storage buffer index utilizing an identifier for said designated one of a plurality of general purpose registers.
Claim 8
Dependent Claim
105 words
The system for enhanced instruction dispatch efficiency in a superscalar processor system of claim 4, wherein said means for storing a relationship between each one of said plurality of intermediate storage buffers and a designated one of a plurality of general purpose registers in a storage buffer index comprises means for storing an identifier for said designated one of said plurality of general purpose registers in said storage buffer index, and means for accessing said identifier for said designated one of said plurality of general purpose registers from said storage buffer index utilizing an identifier for each one of said plurality of intermediate storage buffers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-12 | 1999-08-14 | 2000-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-12 | 2003-08-14 | 2004-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-12 | 2007-08-14 | 2008-02-13 | $7700.00 | Window Closed / Lapsed |