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US5654914A
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Memory cell array semiconductor integrated circuit device
Assignee: Renesas Electronics Corp
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Filing: 1995-06-06
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Granted: 1997-08-05
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Expires: 2015-06-06
Abstract
Abstract Memory cells having a stable write operation are formed in an array on a CMOS gate array semiconductor substrate. Each memory cell includes mutually adjacent transistors from a first pair of complementary conductivity type MOS transistor rows. These transistors are used to form a flip-flop and first and second access gates. The memory cell further includes mutually adjacent MOS transistors from a second pair of complementary conductivity type MOS transistor rows. These transistors are used to form an inverter and a third access gate connected to the output of the inverter. The input of the inverter is connected to one end of the flip-flop. The inputs of the first and second access gates are connected to bit lines through which complementary data signals are applied. The gates of the first and second access gate transistors are connected to a write word line. The third access gate is connected to a read-out signal providing bit line, and the gate of the third access gate MOS transistor is connected to a read word line.
Inventors
- 👤 Koji Nii
- 👤 Hideshi Maeno
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 11:53
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
415 words
A memory cell array semiconductor integrated circuit device comprising: a CMOS gate array semiconductor substrate including a plurality of pairs of MOS transistor rows; a first transistor row in each pair including a plurality of P-channel MOS transistors each sharing source/drain regions with MOS transistors adjacent thereto; a second transistor row in each pair including a plurality of N-channel MOS transistors each sharing source/drain regions with MOS transistors adjacent thereto; a memory cell array including a plurality of memory cells arranged in rows and columns being formed of said MOS transistors on said substrate; said CMOS gate array semiconductor substrate including further a first write word line and a second read word line, a first bit line for supplying a data signal to be written into said memory cells, a second bit line for supplying a signal complementary to said data signal, and a third bit line for providing a read-out signal; first and second inverters connected in loop to form a flip-flop, each of said first and second inverters including a combination of P-channel and N-channel MOS transistors from one of said pairs of MOS transistor rows; a first access gate including a MOS transistor from said one transistor row pair, said first access gate MOS transistor having a drain connected to one of input/output ends of said flip-flop, a source connected to said first bit line and a gate connected to said first word line; a second access gate including a MOS transistor in said one transistor row pair, said second access gate MOS transistor having a drain connected to the other of input/output ends of said flip-flop, a source connected to said second bit line, and a gate connected to said first word line; a third inverter including a combination of P-channel and N-channel MOS transistors from another of said MOS transistor row pairs, said third inverter having its input end connected to said one input/output end of said flip-flop; a third access gate including a MOS transistor from said another MOS transistor row pair, said third access gate MOS transistor having a drain connected to an output end of said third inverter, a source connected to said third bit line, and a gate connected to said second word line; said first, second and third bit lines being common to a plurality of memory cells in the same memory cell row; and said first and second word lines being common to a plurality of memory cells in the same memory cell column.
Claim 2
Dependent Claim
415 words
A memory cell array semiconductor integrated circuit device comprising: a CMOS gate array semiconductor substrate including a plurality of pairs of MOS transistor rows; a first transistor row in each pair including a plurality of P-channel MOS transistors each sharing source/drain regions with MOS transistors adjacent thereto; a second transistor row in each pair including a plurality of N-channel MOS transistors each sharing source/drain regions with MOS transistors adjacent thereto; a memory cell array including a plurality of memory cells arranged in rows and columns being formed of said MOS transistors on said substrate; said CMOS gate array semiconductor substrate including further a first write word line and a second read word line, a first bit line for supplying a data signal to be written into said memory cells, a second bit line for supplying a signal complementary to said data signal, and a third bit line for providing a read-out signal; first and second inverters connected in loop to form a flip-flop, each of said first and second inverters including a combination of P-channel and N-channel MOS transistors from one of said pairs of MOS transistor rows; a first access gate including a MOS transistor from said one transistor row pair, said first access gate MOS transistor having a drain connected to one of input/output ends of said flip-flop, a source connected to said first bit line and a gate connected to said first word line; a second access gate including a MOS transistor in said one transistor row pair, said second access gate MOS transistor having a drain connected to the other of input/output ends of said flip-flop, a source connected to said second bit line, and a gate connected to said first word line; a third inverter including a combination of P-channel and N-channel MOS transistors from another of said MOS transistor row pairs, said third inverter having its input end connected to said one input/output end of said flip-flop; a third access gate including a MOS transistor from said another MOS transistor row pair, said third access gate MOS transistor having a drain connected to an output end of said third inverter, a source connected to said third bit line, and a gate connected to said second word line; said first, second and third bit lines being common to a plurality of memory cells in the same memory cell row; and said first and second word lines being common to a plurality of memory cells in the same memory cell column.
Claim 3
Dependent Claim
78 words
The memory cell array semiconductor integrated circuit device according to claim 1 wherein the first access gates of all of said memory cells in said array include MOS transistors having the same type conductivity channel, the MOS transistor of the first access gate of each memory cell in each memory cell row sharing the source region with the MOS transistor of the first access gate of a memory cell adjacent to that memory cell on one side thereof.
Claim 4
Dependent Claim
78 words
The memory cell array semiconductor integrated circuit device according to claim 1 wherein the second access gates of all of said memory cells in said array include MOS transistors having the same type conductivity channel, the MOS transistor of the second access gate of each memory cell in each memory cell row sharing the source region with the MOS transistor of the second access gate of a memory cell adjacent to that memory cell on one side thereof.
Claim 5
Dependent Claim
79 words
The memory cell array semiconductor integrated circuit device according to claim 2 wherein the second access gates of all of said memory cells in said array include MOS transistors having the same type conductivity channel, the MOS transistor of the second access gate of each memory cell in each memory cell row sharing the source region with the MOS transistor of the second access gate of a memory cell adjacent to that memory cell on the other side thereof.
Claim 6
Dependent Claim
78 words
The memory cell array semiconductor integrated circuit device according to claim 1 wherein the third access gates of all of said memory cells in said array include MOS transistors having the same type conductivity channel, the MOS transistor of the third access gate of each memory cell in each memory cell row sharing the source region with the MOS transistor of the third access gate of a memory cell adjacent to that memory cell on one side thereof.
Claim 7
Dependent Claim
78 words
The memory cell array semiconductor integrated circuit device according to claim 2 wherein the third access gates of all of said memory cells in said array include MOS transistors having the same type conductivity channel, the MOS transistor of the third access gate of each memory cell in each memory cell row sharing the source region with the MOS transistor of the third access gate of a memory cell adjacent to that memory cell on one side thereof.
Claim 8
Dependent Claim
78 words
The memory cell array semiconductor integrated circuit device according to claim 3 wherein the third access gates of all of said memory cells in said array include MOS transistors having the same type conductivity channel, the MOS transistor of the third access gate of each memory cell in each memory cell row sharing the source region with the MOS transistor of the third access gate of a memory cell adjacent to that memory cell on one side thereof.
Claim 9
Dependent Claim
78 words
The memory cell array semiconductor integrated circuit device according to claim 4 wherein the third access gates of all of said memory cells in said array include MOS transistors having the same type conductivity channel, the MOS transistor of the third access gate of each memory cell in each memory cell row sharing the source region with the MOS transistor of the third access gate of a memory cell adjacent to that memory cell on one side thereof.
Claim 10
Dependent Claim
112 words
The memory cell array semiconductor integrated circuit device according to claim 1 wherein, in each of said memory cells, the P-channel and N-channel MOS transistors of said first inverter are disposed adjacent to the P-channel and N-channel MOS transistors of said second inverter, respectively, with respective ones of their source/drain regions shared therewith; the MOS transistor of said first access gate is disposed adjacent to one of the MOS transistors of said first inverter with one of its source/drain regions shared therewith; and the MOS transistor of said second access gate is disposed adjacent to one of the MOS transistors of said second inverter with one of its source/drain regions shared therewith.
Claim 11
Dependent Claim
124 words
The memory cell array semiconductor integrated circuit device according to claim 1, wherein two memory cells in one column of said memory cell array comprise MOS transistors in first, second and third ones of said MOS transistor row pairs; the MOS transistors of said first and second inverters and said first and second access gates of one of said two memory cells are in said first MOS transistor row pair; the MOS transistors of said first and second inverters and said first and second access gates of the other memory cell are in said second MOS transistor row pair; and the MOS transistors of said third inverters and said third access gates of both memory cells are in said third MOS transistor row pair.
Claim 12
Dependent Claim
30 words
The memory cell array semiconductor integrated circuit device according to claim 1 wherein the inverters and access gates of adjacent memory cells in the same memory cell row are symmetrical.
Claim 13
Dependent Claim
54 words
The memory cell array semiconductor integrated circuit device according to claim 1 wherein said third inverter of each memory cell further comprises a combination of a parallel connection of a plurality of MOS transistors of first type conductivity channel and a parallel connection of a plurality of MOS transistors of second type conductivity channel.
Claim 14
Dependent Claim
60 words
The memory cell array semiconductor integrated circuit device according to claim 1 wherein said third inverter of each memory cell further comprises a combination of one MOS transistor of the same type conductivity channel as the MOS transistor of said third access gate of said memory cell and a parallel connection of two MOS transistors of different type conductivity channel.
Claim 15
Dependent Claim
177 words
A memory cell array comprising: first, second, third, and fourth transistor rows; at least first and second memory cells; each memory cell including a flip-flop having first and second inputs and an output; each memory cell including first means for connecting a first bit line to said first input responsive to a write command; each memory cell including second means for connecting a second bit line to said second input responsive to said write command; each memory cell including four adjacent transistors on said first transistor row and two adjacent transistors on said second transistor row; each of said four adjacent transistors sharing a common source/drain region with an adjacent one of said four transistors; each of said two adjacent transistors sharing a common source/drain region; each memory cell including an inverter formed from a transistor from each of said third and fourth transistor rows; each inverter having a third input connected with said output from said flip-flop; and each memory cell including means for reading a data signal from said inverter responsive to a read command.
Claim 16
Dependent Claim
177 words
A memory cell array comprising: first, second, third, and fourth transistor rows; at least first and second memory cells; each memory cell including a flip-flop having first and second inputs and an output; each memory cell including first means for connecting a first bit line to said first input responsive to a write command; each memory cell including second means for connecting a second bit line to said second input responsive to said write command; each memory cell including four adjacent transistors on said first transistor row and two adjacent transistors on said second transistor row; each of said four adjacent transistors sharing a common source/drain region with an adjacent one of said four transistors; each of said two adjacent transistors sharing a common source/drain region; each memory cell including an inverter formed from a transistor from each of said third and fourth transistor rows; each inverter having a third input connected with said output from said flip-flop; and each memory cell including means for reading a data signal from said inverter responsive to a read command.
Claim 17
Dependent Claim
53 words
A memory cell array according to claim 14, further comprising: said four adjacent transistors of said at least first and second memory cells including first and second end transistors; and said first end transistor of said first memory cell sharing a source/drain region with said first end transistor of said second memory cell.
Claim 18
Dependent Claim
53 words
A memory cell array according to claim 14, further comprising: said four adjacent transistors of said at least first and second memory cells including first and second end transistors; and said second end transistor of said first memory cell sharing a source/drain region with said second end transistor of said second memory cell.
Claim 19
Dependent Claim
32 words
A memory cell array according to claim 14, wherein at least one transistor in said first memory cell shares its source/drain region with at least one transistor in said second memory cell.
Claim 20
Dependent Claim
20 words
A memory cell array according to claim 14, wherein said first memory cell is symmetrical to said second memory cell.
Claim 21
Dependent Claim
43 words
A memory cell array according to claim 14 wherein: said means for reading in each memory cell includes a read transistor; and said read transistor of said first memory cell shares a source/drain region with said read transistor of said second memory cell.
Claim 22
Dependent Claim
31 words
A memory cell array according to claim 19, wherein: each read transistor is disposed in said third transistor row; and each read transistor shares a source/drain region with its respective inverter.
Claim 23
Dependent Claim
170 words
A memory cell array, comprising: at least first, second, third, and fourth transistor rows; at least first and second memory cells; each memory cell including a flip-flop having first and second inputs and an output; each memory cell including first means for connecting a first bit line to said first input responsive to a write command; each memory cell including second means for connecting a second bit line to said second input responsive to said write command; said first and second means for connecting and said flip-flop being formed from adjacent transistors of said first and second transistor rows whereby isolating transistors are not required; each memory cell including a buffer invertor having a third input connected with said output; each memory cell including means for reading said data signal from said invertor responsive to a read command; said buffer invertor and said means for reading each having an adjacent transistor in a same transistor row; and said adjacent transistors being in one of said third and fourth transistor rows.
Claim 24
Dependent Claim
170 words
A memory cell array, comprising: at least first, second, third, and fourth transistor rows; at least first and second memory cells; each memory cell including a flip-flop having first and second inputs and an output; each memory cell including first means for connecting a first bit line to said first input responsive to a write command; each memory cell including second means for connecting a second bit line to said second input responsive to said write command; said first and second means for connecting and said flip-flop being formed from adjacent transistors of said first and second transistor rows whereby isolating transistors are not required; each memory cell including a buffer invertor having a third input connected with said output; each memory cell including means for reading said data signal from said invertor responsive to a read command; said buffer invertor and said means for reading each having an adjacent transistor in a same transistor row; and said adjacent transistors being in one of said third and fourth transistor rows.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-04 | 2001-02-03 | 2001-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-04 | 2005-02-03 | 2005-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-04 | 2009-02-03 | 2009-08-05 | $7700.00 | Window Closed / Lapsed |