EP0511401A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory
Assignee: Fujitsu Ltd
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Filing: 1991-11-19
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Granted: —
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Expires: 2011-11-19
Abstract
Abstract A semiconductor memory comprising a memory section (consisting of INV1 through INV4 and Tn1 through Tn4), two write-only bit lines (WBL and WBL ¯ ) for writing data in the memory section, two read-only bit lines (RBL and RBL ¯ ) for reading data from the memory section, and a shorting circuit (50) for shorting the two read-only bit lines to set them to the same potential in the write mode for writing data in the memory section through the write-only bit lines. Data can be read at a high speed from the same address immediately after data is written because the shorting circuit is provided.
Inventors
- 👤 Junichi Shikatani
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 09:07
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
115 words
A semiconductor memory device characterized in that there are provided: a memory part (INV1-INV4, Tn1-Tn4); two bit lines (WBL, WBL ¯ ) exclusively for writing, coupled to said memory part, and used when writing information in said memory part; two bit lines (RBL, RBL ¯ ) exclusively for reading, coupled to said memory part, and used when reading the information held in said memory part; and a short-circuiting circuit (50), coupled to said bit lines exclusively for reading, for short-circuiting said two bit lines exclusively for reading and for setting them to the same potential in a write mode in which information is written into said memory part via said bit lines exclusively for writing.
Claim 2
Dependent Claim
160 words
The semiconductor memory device as claimed in claim 1, characterized in that: the semiconductor memory device is further provided with a word line (WWL) exclusively for writing and a word line (RWL) exclusively for reading respectively coupled to the memory part (INV1-INV4, Tn1-Tn4), and that the memory part includes a flip-flop (FF) having input and output ends of two inverters INV1 and INV2 respectively cross connected, two switching transistors (Tn1, Tn2) respectively connected to two output ends of the flip-flop (FF) and the two write bit lines (WBL, WBL ¯ ) exclusively for writing and having gates connected to said word line (WWL) exclusively for writing, two inverters (INV3, INV4) for inverting outputs from the two output ends of said flip-flop (FF), and two switching transistors (Tn3, Tn4) respectively connected to said inverters (INV3, INV4) and the two read bit lines (RBL, RBL ¯ ) exclusively for reading and having gates connected to said word line (RWL) exclusively for reading.
Claim 3
Dependent Claim
64 words
The semiconductor memory device as claimed in claim 1, characterized in that there is further provided a sense amplifier circuit (1) for reading the information by amplifying a potential difference of said bit lines exclusively for reading in a read mode in which the information is read from the memory part (INV1-INV4, Tn1-Tn4) via the bit lines (RBL, RBL ¯ ) exclusively for reading.
Claim 4
Dependent Claim
56 words
The semiconductor memory device as claimed in claim 1, characterized in that there is further provided a write amplifier circuit (2) for supplying to the bit lines (WBL, WBL ¯ ) exclusively for writing the information to be written into the memory part (INV1-INV4, Tn1-Tn4) in response to a write enable signal in the write mode.
Claim 5
Dependent Claim
34 words
The semiconductor memory device as claimed in claim 4, characterized in that the short-circuiting circuit (50) short-circuits the bit lines (RBL, RBL ¯ ) exclusively for reading in response to the write enable signal.
Claim 6
Dependent Claim
62 words
The semiconductor memory device as claimed in claim 1, characterized in that there is further provided an address transition detection circuit (7) for outputting a predetermined pulse when a transition of an address signal is detected, and a setting circuit (10, T PC2 ) for short-circuiting the bit lines (RBL, RBL ¯ ) exclusively for reading in response to said predetermined pulse.
Claim 7
Dependent Claim
78 words
The semiconductor memory device as claimed in claim 6, characterized in that the short-circuiting circuit (50) and the setting circuit (10, T PC2 ) set the bit lines (RBL, RBL ¯ ) exclusively for reading to the same potential regardless of an immediately preceding mode with respect to the same address in an initial state of a read mode in which the information is read from the memory part (INV1-INV4, Tn1-Tn4) via said bit lines exclusively for reading.
References Cited (Backward Citations)
No citation records indexed.
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