Memory cell circuit for semiconductor integrated circuit device

Abstract

Abstract PURPOSE:To remove useless transistors (TRs) on a gate array and to easily execute layout design by using the same number of N-channle MOS TRs and P-channel MOS TRs. CONSTITUTION:The above memory cell circuit consists of two inverter circuits 1a, 1b, two N-channel MOS TRs 2a, 2b and two P-channel MOS TRs 3c, 3d and the outputs of respectively inverter circuits 1a, 1b are mutually connected to the inputs of the other inverters 1b, 1a to constitute a data holding loop. The memory cell circuit can be constituted of four N-channel MOS TRs and four P-channel MOS TRs. Thereby, when a word line, the inverse of WL2, is set up to an 'L' level, the P-channel MOS TRs 3c, 3d are turned on and data are read out to bit wire pair BIT2, the inverse of BIT2.

Inventors

• 👤 Hideshi Maeno
• 👤 秀史 前野

Bibliographic Details