Patent US5652530A successfully refreshed from Google Patents.
US5652530A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for reducing clock-data skew by clock shifting
Assignee: Intel Corp
•
Filing: 1995-09-29
•
Granted: 1997-07-29
•
Expires: 2015-09-29
Abstract
Abstract A data signal is input into an integrated circuit and the data signal is transmitted through a series of logic gates that cause a propagation delay. An external clock line associated with the data signal is also inputted into the integrated circuit. The external clock signal is passed through a delay shifter that adds a controllable amount of delay to the clock signal. The amount of delay added to the clock signal should equal the total amount of propagation delay added to the data signal. The clock signal is then also transmitted through a phase-lock loop to stabilize the clock signal. The delayed internal clock signal is then used to clock the data signal which has been transmitted through a series of logic gates that have added propagation delay. Since the internal clock signal has been delayed an equal amount as the data signal, the data signal will be clocked at an appropriate time.
Inventors
- 👤 Roni Ashuri
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:29
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00323; G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H03K5/00; H03K5/13; H04; H04L; H04L7/00; H04L7/0008; H04L7/0016; H04L7/0033; H04L7/0037
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
72 words
An electrical circuit, said electrical circuit comprising the elements of: a data path circuit, said data path circuit comprising the subelements of, one or more logic circuits, said logic circuits introducing propagation delay into said data path circuit; a sampling circuit; and a clock circuit for driving said sampling circuit, said clock circuit comprising a delay shifter circuit, said delay shifter circuit introducing a delay time approximately equal to said propagation delay.
Claim 2
Dependent Claim
72 words
An electrical circuit, said electrical circuit comprising the elements of: a data path circuit, said data path circuit comprising the subelements of, one or more logic circuits, said logic circuits introducing propagation delay into said data path circuit; a sampling circuit; and a clock circuit for driving said sampling circuit, said clock circuit comprising a delay shifter circuit, said delay shifter circuit introducing a delay time approximately equal to said propagation delay.
Claim 3
Dependent Claim
22 words
The electrical circuit as claimed in claim 1 wherein said delay shifter circuit comprises at least one capacitor coupled to a ground.
Claim 4
Dependent Claim
27 words
The electrical circuit as claimed in claim 2 wherein said delay shifter circuit further comprises a fuse coupled to each said capacitor, said fuse being individually addressable.
Claim 5
Dependent Claim
15 words
The electrical circuit as claimed in claim 1 wherein said sampling circuit comprises a flip-flop.
Claim 6
Dependent Claim
18 words
The electrical circuit as claimed in claim 1 wherein said clock circuit further comprises a phase locked loop.
Claim 7
Independent Claim
93 words
A method for compensating for propagation delays in a data path, said method comprising the steps of: passing a data signal through a data path comprising at least one logic gate, said data path introducing propagation delay onto said data signal, said data signal having an associated clock signal; delay shifting said clock signal with a delay circuit to produce a delayed clock signal, said delayed clock signal delayed by a delay time approximately equal to said propagation delay; and sampling said data signal, said data signal sampled with said delayed clock signal.
Claim 8
Independent Claim
93 words
A method for compensating for propagation delays in a data path, said method comprising the steps of: passing a data signal through a data path comprising at least one logic gate, said data path introducing propagation delay onto said data signal, said data signal having an associated clock signal; delay shifting said clock signal with a delay circuit to produce a delayed clock signal, said delayed clock signal delayed by a delay time approximately equal to said propagation delay; and sampling said data signal, said data signal sampled with said delayed clock signal.
Claim 9
Dependent Claim
22 words
The method for compensating for propagation delays as claimed in claim 6 wherein said associated clock signal is an external clock signal.
Claim 10
Dependent Claim
37 words
The method for compensating for propagation delays as claimed in claim 6 further comprising the steps of setting said delay time by burning fuses that couple said clock signal to a ground through a plurality of capacitors.
Claim 11
Dependent Claim
96 words
An electrical circuit, said electrical circuit comprising the elements of: a data input; a clock input for receiving a clock signal; a data path circuit coupled to said data input, said data path generating a data output, said data path circuit introducing propagation delay; a sampling circuit, said sampling circuit sampling said data output; and a clock shifter circuit coupled to said clock input, said clock shifter circuit introducing a delay time approximately equal to said propagation delay into said clock signal to produce a delayed clock signal, said delayed clock signal driving said sampling circuit.
Claim 12
Dependent Claim
96 words
An electrical circuit, said electrical circuit comprising the elements of: a data input; a clock input for receiving a clock signal; a data path circuit coupled to said data input, said data path generating a data output, said data path circuit introducing propagation delay; a sampling circuit, said sampling circuit sampling said data output; and a clock shifter circuit coupled to said clock input, said clock shifter circuit introducing a delay time approximately equal to said propagation delay into said clock signal to produce a delayed clock signal, said delayed clock signal driving said sampling circuit.
Claim 13
Dependent Claim
22 words
The electrical circuit as claimed in claim 9 wherein said clock shifter circuit comprises at least one capacitor coupled to a ground.
Claim 14
Dependent Claim
27 words
The electrical circuit as claimed in claim 10 wherein said clock shifter circuit further comprises a fuse coupled to each said capacitor, said fuse being individually addressable.
Claim 15
Dependent Claim
15 words
The electrical circuit as claimed in claim 9 wherein said sampling circuit comprises a flip-flop.
Claim 16
Dependent Claim
26 words
The electrical circuit as claimed in claim 9 wherein said electrical circuit further comprises a phase locked loop, said phased locked loop stabilizing said clock signal.
References Cited (Backward Citations)
US4358741A
Cited
US4814640A
Cited
US4839907A
Cited
US5361277A
Cited
US5043596A
Cited
US5122693A
Cited
US5259006A
Cited
US5283631A
Cited
US5307381A
Cited
US5432823A
Cited
US5572557A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-28 | 2001-01-27 | 2001-07-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-28 | 2005-01-27 | 2005-07-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-28 | 2009-01-27 | 2009-07-29 | $7700.00 | Window Closed / Lapsed |