Serial-to-parallel converter using alternating latches and interleaving techniques

Claim 1

A structure comprising: a bit stream having a bit rate; a first clock at half said bit rate; a second clock at half said bit rate; said first clock selects a first group of N bits from said bit stream; said second clock selects a second group of N bits from said bit stream; said first clock is out of phase with respect to said second clock so that the first group of N bits and said second group of N bits are alternately selected from said bit stream; first means for storing said first group of N bits and said second group of N bits comprising 2N storage cells, a first set of N cells of said 2N storage cells are clocked by said first clock, a second group N cells of said 2N storage cells are docked by said second clock; means clocked by said first clock for placing said first group of N bits into said first means for storing N bits of said bit stream by initially placing the first bit of said first group of N bits into one cell of said first group of N cells; means for sequentially transferring each of said first group of N bits from said one cell of said first group of N cells to a cell from said second group of N cells and sequentially therefrom to another cell of said first group of N cells, such sequential transfer from a cell of said first group of N cells to a cell from said second group of N cells being repeated until said first group of N bits are stored in said first storage location in said first group of N cells; means clocked by said second clock for placing said second group of N bits into said first means for storing N bits of said bit stream by initially placing the first bit of said second group of N bits into one cell of said second group of N cells; means for sequentially transferring each of said second group of N bits from said one cell of said second group of N cells to a cell from said first group of N cells and sequentially therefrom to another cell of said second group of N cells, such sequential transfer from a cell of said second group of N cells to a cell from said first group of cells being repeated until said second group of N bits are stored in said first storage location in said second group of N cells; means for transferring said first group of N bits in unison from said first means for storing into a second means for storing clocked by a third clock; said third clock is substantially congruent with said second clock except that after each phase of said third clock there is missing N-1 pulses of said second clock; means for transferring said second group of N bits in unison from said first means for storing into said second means for storing clocked by a fourth clock; said second group of N bits being transferred from said first means for storing to said second means for storing N bits of said bit stream after said first group of N bits are transferred from said first means for storing to said second means for storing; said fourth clock is substantially identical to said third clock but delayed with respect to said third clock by N bit intervals and its pulses are substantially congruent with said first clock; means for transferring said first group of N bits from said second means for storing substantially in unison to a third means for storing having N cells; means for transferring, substantially in unison, said first group of N bits from said third means for storing to a first group of N cells of a fourth means for storing having 2N cells; means for transferring said second group of N bits, substantially in unison, from said second means for storing to a second group of N cells of said fourth means for storing; means for maintaining said first group of N bits in said third for means for storing for more than N bit intervals of said bit stream so that said transfer of said first group of N bits to said fourth means for storage is substantially in unison with said transfer of said second group of N bits from said second means for storing to said fourth storage means.