Bus interface unit

Claim 2

A bus interface unit for interfacing a serial bit data bus to a parallel bit data handing system, comprising a parallel to serial data converter for converting parallel data from said parallel bit data handing system to serial data; a parity tester responsive to the parity of said parallel data, said parity tester producing an output signal indicative of whether parity of the converted serial data is correct; a frame check sequence generator for generating a frame check sequence in response to content of said serial data and said output signal, said frame check sequence being correct if the parity of said data is correct and other than correct if the parity of said data is incorrect; and output means for outputting the serial data and the frame check sequence to said serial data bus.

Claim 3

A frame check sequence generator comprising: a plurality of shift registers for producting shifted output data, said shift registers including a first shift register and successive shift registers; an input data selector means for selecting input data for said first shift register; a successive data selector means for each of said successive shift registers, each successive data selector being for selecting data to be input to a next one of said successive shift registers, each successive data selector means having a first input for receiving said input data, and a second input; cross connecting means for each successive data selector means, said cross connecting means being for connecting shifted output data from one of said shift registers to said second input of a one of said successive data selectors associated with the next successive shift register: and control means responsive to shifted output data from a last of said successive shift registers for controlling said input data selector means and for controlling said successive data selector means to connect one of said input data and said shifted output data from a previous of said shift registers as input to one of said successive shift registers.

Claim 4

A frame check sequence generator comprising: a plurality of shift registers for producting shifted output data, said shift registers including a first shift register and successive shift registers; an input data selector means for selecting input data for said first shift register; a successive data selector means for each of said successive shift registers, each successive data selector being for selecting data to be input to a next one of said successive shift registers, each successive data selector means having a first input for receiving said input data, and a second input; cross connecting means for each successive data selector means, said cross connecting means being for connecting shifted output data from one of said shift registers to said second input of a one of said successive data selectors associated with the next successive shift register: and control means responsive to shifted output data from a last of said successive shift registers for controlling said input data selector means and for controlling said successive data selector means to connect one of said input data and said shifted output data from a previous of said shift registers as input to one of said successive shift registers.

Claim 5

A bus interface unit for interfacing a serial bit data bus to a parallel bit data handling system, comprising a receiver means for acquiring serial data from said bus, said serial data containing a frame check sequence; a clock means for generating a clock signal at a frequency equal to a frequency of bits in said serial data; a clock processor means for receiving said serial data and said clock signal to generate a clock processor signal for processing said serial data; a serial to parallel data conversion means responsive to said serial data and said clock processor signal for converting said serial data to parallel bit data; an output means for outputting said parallel bit data to said parallel bit data handling system; and a frame check sequence tester responsive to said serial data and said clock processor signal for providing a validity output signal when said frame check sequence is recognized by said tester, said frame check sequence tester including a plurality of parallel path operating means and check means for using a cyclic redundancy code to determine validity of the serial bit data, said check means being a shift register circuit configured to implement the polynomial X.sup.16 +X.sup.12 +X.sup.5 +1, said frame check sequence tester comprising a plurality of shift registers for producing shifted output data, said shift registers including a first shift register and successive shift registers, an input data selector means for selecting input data for said first shift register, a successive data selector means for each of said successive shift registers, each successive data selector being for selecting data to be input to a next one of said successive shift registers, each successive data selector means having a first input for receiving said input data, and a second input, cross connecting means for each successive data selector means, said cross connecting means being for connecting shifted output data from one of said shift registers to said second input of a one of said successive data selectors associated with the next-successive shfit register, and control means responsive to shifted output data from a last of said successive shift registers for controlling said input data selector means to connect one of said input data and said shifted output data from a previous of said shift registers as input to one of said successive shift registers.

Claim 6

A bus interface unit for interfacing a serial bit data bus to a parallel bit data handling system, comprising a receiver means for acquiring serial data from said bus, said serial data containing a frame check sequence; a clock means for generating a clock signal at a frequency equal to a frequency of bits in said serial data; a clock processor means for receiving said serial data and said clock signal to generate a clock processor signal for processing said serial data; a serial to parallel data conversion means responsive to said serial data and said clock processor signal for converting said serial data to parallel bit data; an output means for outputting said parallel bit data to said parallel bit data handling system; and a frame check sequence tester responsive to said serial data and said clock processor signal for providing a validity output signal when said frame check sequence is recognized by said tester, said frame check sequence tester including a plurality of parallel path operating means and check means for using a cyclic redundancy code to determine validity of the serial bit data, said check means being a shift register circuit configured to implement the polynomial X.sup.16 +X.sup.12 +X.sup.5 +1, said frame check sequence tester comprising a plurality of shift registers for producing shifted output data, said shift registers including a first shift register and successive shift registers, an input data selector means for selecting input data for said first shift register, a successive data selector means for each of said successive shift registers, each successive data selector being for selecting data to be input to a next one of said successive shift registers, each successive data selector means having a first input for receiving said input data, and a second input, cross connecting means for each successive data selector means, said cross connecting means being for connecting shifted output data from one of said shift registers to said second input of a one of said successive data selectors associated with the next-successive shfit register, and control means responsive to shifted output data from a last of said successive shift registers for controlling said input data selector means to connect one of said input data and said shifted output data from a previous of said shift registers as input to one of said successive shift registers.

Claim 7

The apparatus of claim 3, further comprising a parity generator for generating a parity bit representative of the parity of said parallel bit data.

Claim 8

The apparatus of claim 3, further comprising transmission means for placing said serial data received from same data bus back on said data bus, said transmission means comprising a timing control responsive to said clock signal for producing timing signals; an output data selector responsive to said timing signals and said serial data for producing a serial data train; and a transmitter responsive to said serial data train for placing said data train on said serial bit data bus.

Claim 9

The apparatus of claim 3, further comprising a timing control responsive to said clock signal for producing timing signals; an input means for receiving input parallel bit data from said data handling system; a parallel to serial converter responsive to said timing signals and said input parallel bit data for converting said input parallel bit data into converted serial data; and a transmission means for placing said converted serial data on said data bus.

Claim 10

The apparatus of claim 6, further comprising a parity tester responsive to said timing signals and said input parallel bit data for testing the parity of said converted serial data and for providing a parity output indicative of whether said parity is correct.

Claim 11

The apparatus of claim 7, further comprising: a frame check sequence generator responsive to said timing signals and said parity output, said frame check sequence generator being for generating a test word, said test word being correct if said parity is correct and incorrect if said parity is in error, and routing means for routing said test word to said transmission means so that said test word is placed on said data bus along with said converted serial data.

Claim 12

The apparatus of claim 8, wherein said frame check sequence generator comprises: a plurality of shift registers for producing shifted output data, said shift registers including a first shift register and successive shift registers; an input data selector means for selecting input data for said first shift register; a successive data selector means for each of said successive shift registers, each successive data selector being for selecting data to be input to a next one of said successive shift registers, each successive data selector means having a first input for receiving said input data, and a second input: cross connecting means for each successive data selector means, said cross connecting means being for connecting shifted output data from one of said shift registers to said second input of a one of said successive data selectors associated with the next successive shift register: and control means responsive to shifted output data from a last of said successive shift registers for controlling said input data selector means and for controlling said successive data selector means to connect one of said input data and said shifted output data from a previous of said shift registers as input to one of said successive shift registers.

Claim 13

The apparatus of claim 8, wherein said frame check sequence generator includes a coding means for impressing a cyclic redundancy code on said test word.

Claim 14

The apparatus of claim 10, wherein said coding means is configured to implement the polynomial: X.sup.16 +X.sup.12 +X.sup.5 +1.

Claim 15

The apparatus of claim 6, wherein said transmission means comprises: a timing control responsive to said clock signal for producing timing signals; and an output data selector responsive to said timing signals and said converted serial data for producing a converted serial data train for transmission by said transmission means.

Claim 16

The apparatus of claim 12, wherein said output data selector has an input for receiving said serial data from said receiver means, and a first forwarding means for forwarding said serial data to said transmission means.

Claim 17

The apparatus of claim 12, further comprising: a parity tester responsive to said timing signals and said converted serial data for testing the parity of said converted serial data and for providing a parity output indicative of whether said parity is correct.

Claim 18

The apparatus of claim 14, further comprising: a frame check sequence generator responsive to said timing signals and said parity output, said frame check sequence generator being for generating a test word, said test word being correct if said parity is correct and incorrect if said parity is in error; and wherein said output data selector has a further input for receiving said test word, and means for forwarding said test word to said transmission means.