Synchronous decoder for self-clocking signals

Claim 2

A synchronous decoder for decoding a self-clocking incoming signal in a packet-type communication system, the synchronous decoder comprising: means for providing a reference clock signal having a clock rate much greater than the clock rate of the incoming signal and for providing a local clock signal independent of the incoming signal and having a clock rate approximately equal to the clock rate of the incoming signal; a shift register, having a plurality of stages, for storing samples of the incoming signal in synchronism with the reference clock signal; means for selecting, at times defined by the local clock signal, a contiguous subset of the samples stored in the shift register from a selected window position of the shift register; means, responsive to the contiguous subset of samples from the shift register, for detecting and accumulating any phase error in the contiguous subset of the samples; and means, responsive to the accumulated phase error, for adjusting the selected window position from which the contiguous samples are selected.

Claim 3

A synchronous decoder as in claim 1 wherein the shift register means has a sufficient number of stages, so that the selected position does not move beyond either a first stage or last stage of the shift register.

Claim 4

A synchronous decoder as in claim 1 wherein the shift register means has a sufficient number of stages, so that if the difference in the clock rate of the reference clock signal and the clock rate of a clock signal embedded in the self-clocking incoming signal is at a maximum expected value, a sufficient number of samples of the incoming signal are stored in the shift register means to accommodate the selected position.

Claim 5

A synchronous decoder as in claim 1 wherein the selecting means includes a funnel selector, connected to the shift register, for providing a window contents value consisting of the sample values from a plurality of contiguous stages of the shift register, the position of the contiguous stages selected thereby being determined by the value of a window pointer register.

Claim 6

A synchronous decoder as in claim 3 wherein the means for adjusting the accumulated phase error additionally comprises: means, connected to receive the average error value, for incrementing or decrementing the window pointer register in accordance with changes in the average error value.

Claim 7

A synchronous decoder as in claim 1 wherein the position of the contiguous stages selected by the selecting means tends to remain in a predetermined position.

Claim 8

A synchronous decoder for decoding a self-clocking incoming signal in a packet-type communication system, the synchronous decoder comprising: means for providing a reference clock signal having a clock rate much greater than the clock rate of the incoming signal and for providing a local clock signal independent of the incoming signal and having a clock rate approximately equal to the clock rate of the incoming signal; a shift register, having a clock input connected to receive the reference clock signal, and a first stage data input connected to receive the incoming signal; a window pointer register containing a window pointer value; funnel selector means, connected to the shift register, for providing a window contents value consisting of the contents, at times defined by the local clock signal, of a plurality of contiguous stages of the shift register, the window position of the contiguous stages selected thereby being determined by the window pointer value; a window contents register containing the window contents value; phase detector means, for determining the location of a level transition as indicated by the values of adjacent bits in the window contents value having complementary logical values, and for providing an error value indicating the relative position of the level transition in the window contents register; filter means, connected to receive successive error values, and to provide an average error value; and means, connected to receive the average error value and to increment or decrement the window pointer in accordance with changes in the average error value, so that the level transition in the window contents register tends to remain in a predetermined position.

Claim 9

A synchronous decoder for decoding a self-clocking incoming signal in a packet-type communication system, the synchronous decoder comprising: means for providing a reference clock signal having a clock rate much greater than the clock rate of the incoming signal and for providing a local clock signal independent of the incoming signal and having a clock rate approximately equal to the clock rate of the incoming signal; a shift register, having a clock input connected to receive the reference clock signal, and a first stage data input connected to receive the incoming signal; a window pointer register containing a window pointer value; funnel selector means, connected to the shift register, for providing a window contents value consisting of the contents, at times defined by the local clock signal, of a plurality of contiguous stages of the shift register, the window position of the contiguous stages selected thereby being determined by the window pointer value; a window contents register containing the window contents value; phase detector means, for determining the location of a level transition as indicated by the values of adjacent bits in the window contents value having complementary logical values, and for providing an error value indicating the relative position of the level transition in the window contents register; filter means, connected to receive successive error values, and to provide an average error value; and means, connected to receive the average error value and to increment or decrement the window pointer in accordance with changes in the average error value, so that the level transition in the window contents register tends to remain in a predetermined position.

Claim 10

A synchronous decoder as in claim 7 wherein the shift register has a sufficient number of stages, so that the selected position does not move beyond either a first stage or last stage of the shift register.

Claim 11

A synchronous decoder as in claim 1 wherein the shift register has a sufficient number of stages, so that if the difference in the clock rate of the reference clock signal and the clock rate of a clock signal embedded in the self-clocking incoming signal is at a maximum expected value, a sufficient number of samples of the incoming signal are stored in the shift register means to accommodate the selected position.

Claim 12

A synchronous decoder as in claim 7 additionally comprising: means for asserting a phase lock signal when the window contents register contains a single level transition.

Claim 13

A synchronous decoder as in claim 7 additionally comprising: means for de-asserting a phase lock signal when either no transitions or multiple transitions are present in the window contents register.

Claim 14

For use in a local area network that interconnects a plurality of devices, the devices transmitting signals over the network to each other, the transmitted signals having a self-clocking signalling format, and the transmitting signals each including data formatted into packets having a maximum time duration, a synchronous decoder for decoding one said transmitted signal received by the decoder as an incoming digital signal, the synchronous decoder comprising: a clock generator, for generating a local clock signal and for generating a frequency divided local clock signal by frequency dividing the local clock signal, the local clock signal being independent of the incoming signal and having a clock rate much greater that the fundamental clock rate of the transmitted signals, and the frequency divided local clock signal having a clock rate approximately the same as the fundamental clock rate of the transmitted signals; a multiple-stage shift register, connected to receive the local clock signal at a clock control input, and connected to receive the incoming digital signal at a first stage input, so that the incoming digital signal is sampled at a rate much greater than its fundamental clock rate; a window pointer register, for storing a window pointer value; funnel selector means, connected to the shift register and the window pointer register, for selecting the sample values from a number of adjacent stages of the shift register, the window location of the adjacent sample values being controlled by the value of the window pointer register, and the number of stages selected thereby corresponding to at least one half the fundamental bit duration of the incoming digital signal; a window contents register, for latching the output of the funnel selector in synchronism with the frequency divided local clock signal; output selector means, connected to the window contents register, for selecting a predetermined sample thereof to provide a decoded output signal; phase detector means, for receiving the output of the window register, and for providing a phase error value dependent upon the position of a transition in the window register as indicated by adjacent samples having complementary values, and for asserting a phase lock signal when the window register contains a single transition, and for de-asserting a phase lock signal when either no transitions or multiple transitions are present in the window register; loop filter means, for averaging the phase error values output by the phase error means, comprising an accumulator which accumulates successive phase error values in synchronism with the frequency-divided local clock signal, and for providing an average phase error value; and means for incrementing the value of the window pointer register when the average phase error indicates that the window register is phase-lagging, and for decrementing the value of the window pointer register when the average phase error value indicates the window register is phase-leading.

Claim 15

For use in a local area network that interconnects a plurality of devices, the devices transmitting signals over the network to each other, the transmitted signals having a self-clocking signalling format, and the transmitting signals each including data formatted into packets having a maximum time duration, a synchronous decoder for decoding one said transmitted signal received by the decoder as an incoming digital signal, the synchronous decoder comprising: a clock generator, for generating a local clock signal and for generating a frequency divided local clock signal by frequency dividing the local clock signal, the local clock signal being independent of the incoming signal and having a clock rate much greater that the fundamental clock rate of the transmitted signals, and the frequency divided local clock signal having a clock rate approximately the same as the fundamental clock rate of the transmitted signals; a multiple-stage shift register, connected to receive the local clock signal at a clock control input, and connected to receive the incoming digital signal at a first stage input, so that the incoming digital signal is sampled at a rate much greater than its fundamental clock rate; a window pointer register, for storing a window pointer value; funnel selector means, connected to the shift register and the window pointer register, for selecting the sample values from a number of adjacent stages of the shift register, the window location of the adjacent sample values being controlled by the value of the window pointer register, and the number of stages selected thereby corresponding to at least one half the fundamental bit duration of the incoming digital signal; a window contents register, for latching the output of the funnel selector in synchronism with the frequency divided local clock signal; output selector means, connected to the window contents register, for selecting a predetermined sample thereof to provide a decoded output signal; phase detector means, for receiving the output of the window register, and for providing a phase error value dependent upon the position of a transition in the window register as indicated by adjacent samples having complementary values, and for asserting a phase lock signal when the window register contains a single transition, and for de-asserting a phase lock signal when either no transitions or multiple transitions are present in the window register; loop filter means, for averaging the phase error values output by the phase error means, comprising an accumulator which accumulates successive phase error values in synchronism with the frequency-divided local clock signal, and for providing an average phase error value; and means for incrementing the value of the window pointer register when the average phase error indicates that the window register is phase-lagging, and for decrementing the value of the window pointer register when the average phase error value indicates the window register is phase-leading.

Claim 16

A synchronous decoder as in claim 12 wherein the multiple-stage shift register has a sufficient number of stages, so that if the difference in the clock rate of the frequency-divided local clock and the fundamental clock rate of the incoming digital signal is at a maximum expected value, a sufficient number of samples of the incoming signal are present in the multiple-stage shift-register, so that the selected position does not move beyond either a first stage or last stage of the shift register.

Claim 19

A method as in claim 14 wherein the shift register has a sufficient number of stages, so that the selected position does not move beyond either a first stage or last stage of the shift register.

Claim 20

A method as in claim 14 wherein the shift register has a sufficient number of stages, so that if the difference in the clock rate of the reference clock signal and the clock rate of a clock signal embedded in the self-clocking incoming signal is at a maximum expected value, a sufficient number of samples of the incoming signal are stored in the shift register to accommodate the selected position.

Claim 21

A method as in claim 14 wherein the shift register has a sufficient number of stages, so that if the difference in the clock rate of the reference clock signal and the clock rate of a clock signal embedded in the self-clocking incoming signal is at a maximum expected value, a sufficient number of samples of the incoming signal are always stored in the shift register means, and so that the selected position does not change beyond either a first stage or last stage of the shift register.

Claim 22

A method as in claim 14 wherein the step of selecting a contiguous subset of samples provides a window contents value consisting of the sample values from a plurality of contiguous stages of the shift register, the position of the contiguous stages selected thereby being determined by the value of a window pointer register.

Claim 23

A method as in claim 14 additionally comprising the step of: incrementing or decrementing the window pointer register in accordance with changes in the average error value, so that the position of the contiguous stage selected thereby tends to remain in a predetermined position.

Claim 24

A method as in claim 19 additionally comprising the steps of: asserting a phase lock signal when the window contents register contains a single transition; and de-asserting a phase lock signal when either no transitions or multiple transitions are present in the window contents register.