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US4653075A Expired / Lapsed US ⏱️ 0.0 years remaining

BPSK synchronizer using computational analysis

Assignee: Lanteris Space LLC
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Filing: 1985-03-29
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Granted: 1987-03-24
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Expires: 2005-03-29
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Abstract

Abstract A bit synchronizer for a BPSK input signal having a sinusoidal carrier frequency f that is much greater than the modulating signal bit rate. The synchronizer comprises means (29, 31) for repetitively sampling the amplitude of the input signal over a preselected sampling interval portion of each modulating signal bit period (T). For each sampling interval, three numbers are recorded: N1, the total number of samples; N2, the number of samples that do not change sign with respect to a reference sample; and N3, the number of samples that do change sign with respect to the reference sample. When the number of samples not changing sign exceeds a preselected threshold value, which takes into account noise corruption of the input signal, bit synchronization is declared, a synchronized output clock (39) is generated, and digital data having a 180° ambiguity is sent to subsequent ambiguity resolution means. When synchronization has not yet occurred, and the last sample changed sign, a phase circuit 34 is adjusted to shift in the proper direction a local clock (38), causing time-shifting of the sampling interval window prior to examination of the next modulating signal bit period (T).

Inventors

  • 👤 Jacob H. Wisniewski

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 09:59
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0334

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 204 words
A BPSK synchronizer for bit synchronizing with an output clock a modulated input signal having a sinusoidal carrier frequency of f and a binary modulating signal, where f is much greater than the modulating signal bit rate, said synchronizer comprising: means for taking several samples of the amplitude of the input signal over a sampling interval portion of each modulating signal bit period, wherein the frequency f is an integral multiple of the rate at which said sampling means samples the amplitude of the input signal; coupled to the sampling means, means for recording, for each sampling interval, the total number of samples, the number of samples that change sign with respect to a reference sample, and the number of samples that do not change sign with respect to the reference sample; coupled to the recording means, means for determining a synchronization condition when, within a sampling interval, the number of samples which have been recorded not to have changed sign exceeds a preselected threshold level; and coupled to the determining means, means for generating an output clock synchronized with the modulated input signal, and having a frequency equal to the modulating signal bit rate, when the determining means has determined a synchronization condition.
Claim 2
Dependent Claim 204 words
A BPSK synchronizer for bit synchronizing with an output clock a modulated input signal having a sinusoidal carrier frequency of f and a binary modulating signal, where f is much greater than the modulating signal bit rate, said synchronizer comprising: means for taking several samples of the amplitude of the input signal over a sampling interval portion of each modulating signal bit period, wherein the frequency f is an integral multiple of the rate at which said sampling means samples the amplitude of the input signal; coupled to the sampling means, means for recording, for each sampling interval, the total number of samples, the number of samples that change sign with respect to a reference sample, and the number of samples that do not change sign with respect to the reference sample; coupled to the recording means, means for determining a synchronization condition when, within a sampling interval, the number of samples which have been recorded not to have changed sign exceeds a preselected threshold level; and coupled to the determining means, means for generating an output clock synchronized with the modulated input signal, and having a frequency equal to the modulating signal bit rate, when the determining means has determined a synchronization condition.
Claim 3
Dependent Claim 21 words
The synchronizer of claim 1 wherein the carrier frequency is at least 16 times greater than the modulating signal bit rate.
Claim 4
Dependent Claim 22 words
The synchronizer of claim 1 wherein the reference sample is the first sample taken by the sampling means during each sampling interval.
Claim 5
Dependent Claim 45 words
The synchronizer of claim 1 wherein the sampling means comprises: an analog-to-digital converter having an input coupled to the input signal; and a sampling clock generator, having an input coupled to the input signal, for producing a clock which oscillates at the desired sampling rate.
Claim 6
Dependent Claim 34 words
The synchronizer of claim 1 wherein the recording means determines whether a given sample has changed sign by multiplying the digitized value of the given sample by the digitized value of the reference sample.
Claim 7
Dependent Claim 40 words
The synchronizer of claim 1 further comprising, coupled to the determining means, means for time-shifting the subsequent sampling interval when the number of samples which have been recorded not to have changed sign does not exceed the preselected threshold level.

References Cited (Backward Citations)

US3551816A Cited
US4146743A Cited
US4290140A Cited
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US4246654A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-03-23 1990-09-22 1991-03-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-03-23 1994-09-22 1995-03-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-03-23 1998-09-22 1999-03-24 $7700.00 Window Closed / Lapsed

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