Digital coherent PSK demodulator and detector

Claim 2

A digital demodulator and detector for digital signals of serially encoded digital bits according to phase shift keying (PSK) utilizing a predetermined carrier frequency and a predetermined bit rate, said digital demodulator and detector, including an oscillator for providing a clock signal, said demodulator and detector comprising: divider means for frequency dividing the clock signal to provide sampling pulses; first sampling means, coupled to the divider means, for digitally sampling the PSK encoded signal in response to each sampling pulse; second sampling means, coupled to the first sampling means, for storing the sample previously taken by the first sampling means; difference detector, coupled to the first and second sampling means, for generating a transition signal in response to a difference between the sample of the first sampling means and the second sampling means; first logic means, coupled to the divider means, for dividing the output of the divider means by two, and generating a subtract loop pulse and an add loop pulse; first digital control means, coupled to the logic means, the difference detector and the divider means for modifying the frequency of the sampling pulses in response to a transition signal such that the sampling pulse frequency is increased in response to the add loop pulse and decreased in response to the subtract loop pulse whereby the sample pulses are synchronized with the carrier; and demodulation means, coupled to the first sampling means, and to the logic means, for generating demodulated baseband signal samples.

Claim 3

The digital demodulator and detector of claim 1, further comprising: programmable divider means, coupled to the divider means, for frequency dividing the sample pulses to provide timing pulses; demodulation buffer means, coupled to the demodulation means, and the logic means, for storing the samples of the demodulated baseband signal; third sampling means, coupled to the programmable divider means, and the demodulation buffer means, for storing the least significant bit of the demodulation buffer means in response to a timing pulse; comparator means, coupled to the demodulation buffer means and the third sampling means, for generating a difference pulse in response to a difference between the stored contents of the third sampling means and the current least significant bit of the demodulation buffer; second logic means, coupled to the programmable divider, for frequency dividing the timing pulses by two and generating a subtract pulse and an add pulse; second digital control means, coupled to the second logic means, and the comparator means, for programming the programmable divider means to increase the time between timing pulses in response to a predetermined number of difference pulses and add pulse, and to decrease the time between timing pulses in response to a predetermined number of difference pulses and subtract pulses, thereby providing bit synchronized timing pulses; synchronized register, coupled to the demodulation buffer and the second logic means, for storing the samples corresponding to one bit of the digital signal in response to a subtract pulse; and majority logic means, for integrating the samples in the synchronized register and generating a detected digital bit output.

Claim 4

The digital demodulator and detector of claim 2, further comprising carrier synchronizing means, coupled to the demodulator buffer means and the first logic means, for storing the contents of the demodulation buffer and shifting right by one sampling in response to the add loop pulse; and whereby the synchronized register is coupled to said carrier synchronizing means.

Claim 5

The digital demodulator and detector of claim 2, further comprising latch means, coupled to the majority logic means, and the second logic means, for latching the output of the majority logic means in response to a subtract pulse.

Claim 6

The digital demodulator and detector of claim 3, further comprising latch means, coupled to the majority logic means, and the second logic means for latching the output of the majority logic means in response to a subtract pulse.

Claim 7

The digital demodulator and detector of claim 1, wherein the divider means provide sampling pulses at a frequency of approximately four times the carrier frequency.

Claim 8

The digital demodulator and detector of claim 5, wherein the divider means provides sampling pulses at a frequency of approximately four times the carrier frequency.

Claim 9

The digital demodulator and detector of claim 1, wherein the first logic means is a T flip-flop.

Claim 10

The digital demodulator and detector of claim 5, wherein the first logic means is a T flip-flop and second logic means is a T flip-flop.

Claim 11

The digital demodulator and detector of claim 9, wherein the divider means provides sampling pulses at a frequency of approximately four times the carrier frequency.

Claim 14

The method of claim 11 further comprising the steps of: a. frequency dividing by a programmable divider means the sample pulses to provide timing pulses; b. storing the samples of the demodulated baseband signal in a demodulation buffer; c. storing in a sample register, the least significant bit of the demodulation buffer in response to a timing pulse; d. generating a difference pulse in response to a difference between the stored contents of the sample register and the current least significant bit of the demodulation buffer; e. frequency dividing the timing pulse by two and generating a subtract pulse and an add pulse; f. programming the programmable divider means to increase the time between timing pulses in response to a predetermined number of difference pulses and add pulses, and to decrease the time between timing pulses in response to a predetermined number of difference pulses and subtract pulses, g. storing in a synchronized register, samples corresponding to one bit of the digital signal in response to a subtract pulse; h. generating a detected digital bit output from the samples of the synchronized register.

Claim 15

The method of claim 12 further comprising the step of: storing the contents of the demodulation buffer and shifting right by one sample in response to the add loop pulse.

Claim 16

The method of claim 13 further comprising the step of latching the detected digital bit output.

Claim 17

The method of claim 11 wherein the step of frequency dividing the clock signal provides timing pulses of approximately four times a predetermined carrier frequency.