US5646904A
Expired / Lapsed
US
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Semicoductor memory with a timing controlled for receiving data at a semiconductor memory module to be accessed
Assignee: Lapis Semiconductor Co Ltd
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Filing: 1995-10-18
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Granted: 1997-07-08
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Expires: 2015-10-18
Abstract
Abstract In a semiconductor memory, a plurality of semiconductor memory modules are connected through a common clock signal line and one or more other signal lines to an accessing circuit. The accessing circuit has a timing information storage unit for storing predetermined access timing information associated with the respective semiconductor memory modules, and a timing varying unit for varying a data receiving timing at a transfer destination in compliance with a semiconductor memory module to be accessed, on the basis of the access timing information stored in the timing information storage unit.
Inventors
- 👤 Yasuhiro Ohno
- 👤 Manabu Miyata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:13
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243; G06F13/14; G06F13/16; G06F13/1668; G06F13/1689; G06F13/1694
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
115 words
A semiconductor memory comprising: a plurality of semiconductor memory modules; a common clock signal line; at least one other common signal line; and an accessing circuit, connected through said common clock signal line and said at least one other common signal line to said plurality of semiconductor memory modules, for accessing said plurality of semiconductor memory modules, said accessing circuit comprising: a timing information storage unit for storing predetermined access timing information associated with each of said semiconductor memory modules; and a timing varying unit for varying a data receiving timing for an accessed one of said plurality of semiconductor memory modules, according to the access timing information stored in said timing information storage unit.
Claim 2
Dependent Claim
115 words
A semiconductor memory comprising: a plurality of semiconductor memory modules; a common clock signal line; at least one other common signal line; and an accessing circuit, connected through said common clock signal line and said at least one other common signal line to said plurality of semiconductor memory modules, for accessing said plurality of semiconductor memory modules, said accessing circuit comprising: a timing information storage unit for storing predetermined access timing information associated with each of said semiconductor memory modules; and a timing varying unit for varying a data receiving timing for an accessed one of said plurality of semiconductor memory modules, according to the access timing information stored in said timing information storage unit.
Claim 3
Dependent Claim
63 words
A semiconductor memory according to claim 1, wherein said accessed one of said plurality of semiconductor memory modules includes means for receiving data and a control signal, and said timing varying unit phase-shifts the data and control signal received by said accessed one of said plurality of semiconductor memory modules, according to the access timing information stored in said timing information storage unit.
Claim 4
Dependent Claim
34 words
A semiconductor memory according to claim 1, wherein said timing varying unit phase-shifts a clock signal on said clock signal line according to the access timing information stored in said timing information storage unit.
Claim 5
Dependent Claim
131 words
A semiconductor memory comprising: a plurality of semiconductor memory modules having respective different operational speeds; a common clock signal line; at least one other common signal line; and an accessing circuit, connected through said common clock signal line and said at least one other common signal line to said plurality of semiconductor memory modules, for accessing said plurality of semiconductor memory modules, said accessing circuit comprising: a timing information storage unit for storing predetermined access timing information associated with each of said semiconductor memory modules; and a clock width varying unit for varying a clock width of a clock signal applied on said common clock signal line to an accessed one of said plurality of semiconductor memory modules, according to the access timing information stored in said timing information storage unit.
Claim 6
Dependent Claim
131 words
A semiconductor memory comprising: a plurality of semiconductor memory modules having respective different operational speeds; a common clock signal line; at least one other common signal line; and an accessing circuit, connected through said common clock signal line and said at least one other common signal line to said plurality of semiconductor memory modules, for accessing said plurality of semiconductor memory modules, said accessing circuit comprising: a timing information storage unit for storing predetermined access timing information associated with each of said semiconductor memory modules; and a clock width varying unit for varying a clock width of a clock signal applied on said common clock signal line to an accessed one of said plurality of semiconductor memory modules, according to the access timing information stored in said timing information storage unit.
Claim 7
Dependent Claim
165 words
A semiconductor memory comprising: a plurality of semiconductor memory modules having respective different operational speeds; a common clock signal line; at least one other common signal line; and an accessing circuit, connected through said common clock signal line and said at least one other common signal line to said plurality of semiconductor memory modules, for accessing said plurality of semiconductor memory modules, said accessing circuit comprising: a timing information storage unit for storing predetermined access timing information associated with each of said semiconductor memory modules; a timing varying unit for varying a data receiving timing for an accessed one of said plurality of semiconductor memory modules, according to the access timing information stored in said timing information storage unit; and a clock width varying unit for varying a clock width of a clock signal applied on said common clock signal line to the accessed one of said plurality of semiconductor memory modules, according to the access timing information stored in said timing information storage unit.
Claim 8
Dependent Claim
165 words
A semiconductor memory comprising: a plurality of semiconductor memory modules having respective different operational speeds; a common clock signal line; at least one other common signal line; and an accessing circuit, connected through said common clock signal line and said at least one other common signal line to said plurality of semiconductor memory modules, for accessing said plurality of semiconductor memory modules, said accessing circuit comprising: a timing information storage unit for storing predetermined access timing information associated with each of said semiconductor memory modules; a timing varying unit for varying a data receiving timing for an accessed one of said plurality of semiconductor memory modules, according to the access timing information stored in said timing information storage unit; and a clock width varying unit for varying a clock width of a clock signal applied on said common clock signal line to the accessed one of said plurality of semiconductor memory modules, according to the access timing information stored in said timing information storage unit.
Claim 9
Dependent Claim
63 words
A semiconductor memory according to claim 5, wherein said accessed one of said plurality of semiconductor memory modules includes means for receiving data and a control signal, and said timing varying unit phase-shifts the data and control signal received by said accessed one of said plurality of semiconductor memory modules, according to the access timing information stored in said timing information storage unit.
Claim 10
Dependent Claim
34 words
A semiconductor memory according to claim 5, wherein said timing varying unit phase-shifts a clock signal on said clock signal line according to the access timing information stored in said timing information storage unit.
Claim 11
Dependent Claim
108 words
A semiconductor memory comprising: a first memory module for access by a first clock signal; a second memory module for access by a second clock signal having a clock width wider than that of the first clock signal, said second memory module having an operational speed slower than an operational speed of said first memory module; and an accessing circuit for providing said first memory module with data and the first clock signal, and said second memory module with data and the second clock signal, said accessing circuit comprising a clock width varying unit for generating the first and second clock signals from a common clock signal input.
Claim 12
Dependent Claim
108 words
A semiconductor memory comprising: a first memory module for access by a first clock signal; a second memory module for access by a second clock signal having a clock width wider than that of the first clock signal, said second memory module having an operational speed slower than an operational speed of said first memory module; and an accessing circuit for providing said first memory module with data and the first clock signal, and said second memory module with data and the second clock signal, said accessing circuit comprising a clock width varying unit for generating the first and second clock signals from a common clock signal input.
Claim 13
Dependent Claim
34 words
A semiconductor memory according to claim 8, wherein said first and second memory modules and said accessing circuit are all connected through a common clock signal line and at least another common signal line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-07 | 2001-01-06 | 2001-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-07 | 2005-01-06 | 2005-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-07 | 2009-01-06 | 2009-07-08 | $7700.00 | Window Closed / Lapsed |