Clock re-generating circuit for system controller

Abstract

Abstract A clock re-generating circuit for a system controller is disclosed. When the system controller makes interface with a peripheral circuit having a lagging operating frequency, the clock periods are varied by generating a slow signal after decoding the address bus generated under the condition. When the system controller operates after receipt of a ready signal from a peripheral circuit, the clock periods are varied in such a manner as not to access to the data by holding the operation of the system controller during a waiting signal is kept active. In this manner, the system controller is kept in the optimum interface state with the peripheral circuits.

Inventors

• 👤 Kyoung Su Kim

Bibliographic Details