EP0479428A1
Expired / Lapsed
EP
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Data processing apparatus for dynamically setting timings in a dynamic memory system
Assignee: International Business Machines Corp
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Filing: 1991-08-30
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Granted: —
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Expires: 2011-08-30
Abstract
Abstract A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.
Inventors
- 👤 Alfredo Aldereguia
- 👤 Daryl Carvis Cromer
- 👤 Patrick Maurice Bland
- 👤 Roger Max Stutes
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 07:06
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243; G06F12/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
226 words
A data processing system comprising: a dynamic read/write memory (14) including at least one memory module (16) having a multiplicity of addressable storage locations; a memory controller (12) for controlling operation of said memory; a processor (10) for initiating memory access cycles to read data from said memory and write data into said memory, said processor being operable to selectively produce accessing signals including cycle definition and address signals to start a memory access cycle; and bus means (30, 32, 36) interconnecting said processor, said memory, and said memory controller to transfer data and accessing signals therebetween; said memory module being operable in response to receiving module operating signals including cycle definition, row address, column address, row address strobe, and column address strobe signals, to read and write data in accordance with said cycle definition signals; said memory controller (12) being operable to transmit said module operating signals to said memory module in response to receiving accessing signals from said processor to start a memory access cycle, characterised in that said memory controller comprises a definition register (40) for storing pulse control signals therein controlling timing of said module operating signals, and a sequencer (80) responsive to said pulse control signals to transmit to said memory module each time said memory is accessed signals the lengths of which are dynamically controlled by said pulse control signals.
Claim 2
Dependent Claim
226 words
A data processing system comprising: a dynamic read/write memory (14) including at least one memory module (16) having a multiplicity of addressable storage locations; a memory controller (12) for controlling operation of said memory; a processor (10) for initiating memory access cycles to read data from said memory and write data into said memory, said processor being operable to selectively produce accessing signals including cycle definition and address signals to start a memory access cycle; and bus means (30, 32, 36) interconnecting said processor, said memory, and said memory controller to transfer data and accessing signals therebetween; said memory module being operable in response to receiving module operating signals including cycle definition, row address, column address, row address strobe, and column address strobe signals, to read and write data in accordance with said cycle definition signals; said memory controller (12) being operable to transmit said module operating signals to said memory module in response to receiving accessing signals from said processor to start a memory access cycle, characterised in that said memory controller comprises a definition register (40) for storing pulse control signals therein controlling timing of said module operating signals, and a sequencer (80) responsive to said pulse control signals to transmit to said memory module each time said memory is accessed signals the lengths of which are dynamically controlled by said pulse control signals.
Claim 3
Dependent Claim
105 words
A data processing system in accordance with claim 1, wherein: said memory (14) comprises a plurality of memory modules (16); and said memory controller (12) comprises a plurality of programmable definition registers (40) each associated with a different one of said memory modules and storing pulse control signals specific to the associated one of said memory modules (16), said memory controller including means (44) operable in response to said accessing signals to select a module to be accessed and transmit to said sequencer (80) pulse control signals read from the one of said definition registers associated with the one of said memory modules so selected.
Claim 4
Dependent Claim
72 words
A data processing system in accordance with claim 2 wherein: one of said memory modules (16) is accessible in accordance with a first set of timing requirements: and another one of said memory modules (16) is accessible in accordance with a second set of timing requirements different than said first set; said definition registers (40) being programmed to provide pulse control signals meeting the timing requirements of both of said memory modules.
Claim 5
Dependent Claim
56 words
A data processing system in accordance with claim 2 or 3 comprising: timing means for producing clock signals each of a fixed clock period and transmitting said clock signals to said controller; said pulse control signals in each definition register specifying the lengths of signals controlled thereby in terms of a number of said clock periods.
Claim 6
Dependent Claim
30 words
A data processing system in accordance with claim 4 wherein: said pulse control signals determine RAS precharge time, RAS to CAS time, and CAS pulse width during memory access cycles.
Claim 7
Dependent Claim
65 words
A data processing system in accordance with claim 2 wherein: said sequencer (80) is operable in response to said controller (12) receiving said accessing signals from said processor to sequence through a series of states including a start state, a RAS precharge state, a RAS to CAS state, and a CAS state during which said operating signals are transmitted to one of said memory modules.
Claim 8
Dependent Claim
67 words
A data processing system in accordance with claim 6 wherein: said controller comprises means responsive to receipt of said accessing signals for controlling said sequencer to cycle through a page miss cycle or a page hit cycle, said page miss cycle being a series of all of said states, said page hit cycle being a series of all of said states except for said RAS precharge state.
Claim 9
Dependent Claim
78 words
A data processing system in accordance with claim 7 wherein: said address signals include a row address, and said controller comprises a comparator (48) for storing an old row address of a row accessed in a preceding memory access, said comparator including an input for receiving a new row address of a storage location to be accessed, and comparing said new address to said old address and outputting in response to such comparison a page hit control signal.
Claim 10
Dependent Claim
47 words
A data processing system in accordance with claim 8 wherein: said page hit signal is produced during said start state and is used to enter said RAS precharge state for a page miss cycle and to enter said RAS to CAs state for a page hit cycle.
Claim 11
Dependent Claim
45 words
A data processing system in accordance with claim 8 wherein: said pulse control signals are read into said sequencer during said RAS precharge state when cycling through a page miss cycle and during said RAS to CAS state when cycling through a page hit cycle.
Claim 12
Dependent Claim
31 words
A data processing system in accordance with claim 10 wherein: said pulse control signals determine the lengths of said RAS precharge state, said RAS to CAS state, and said CAS state.
References Cited (Backward Citations)
US3753232A
Cited
EP0386935A2
Cited
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