Computer mainframe signal monitoring system

Claim 1

A computer mainframe signal monitoring system connected to the mainframe of computer to monitor its signals, comprising a main control circuit, a data catching and processing integrated circuit and a monitor respectively connected to said main control circuit and controlled by it, wherein said monitor is comprised of a LED array and a driver IC, the LEDs of said LED array of said monitor respectively corresponding to the major function signals of a motherboard of the mainframe such as A0-A3, D0-D31, IRQ0-IRQ15, DRQ0-DRQ7, and regular I/O signals such as COM1-COM4, LPT1-LPT3, said driver IC comprising a serial in parallel out register array, a latching logic, and a driver circuit; said catching and processing integrated circuit is comprised of an I/O signal decoding and processing circuit, a control signal catching and delay circuit, a preliminary latching logic, a latching logic, and a parallel in serial out register array, said I/O signal decoding and processing circuit comprised of a decoder circuit and a signal catching and delay circuit, said decoder circuit being connected to an I/O address line of the mainframe to decode its signal and then to send the decoded I/O signal to said signal catching and delay circuit, said signal catching and delay circuit catching the decoded I/O signal from said decoder circuit and then sending it to the latching logic of said data catching and processing integrated circuit after a predetermined time delay, said control signal catching and delay circuit comprised of a control signal catching circuit and a delay circuit, said control signal catching circuit being connected to a control bus of the mainframe to catch the control signal and then to send the caught control signal to said delay circuit, which sends the control signal to the latching logic of said data catching and processing integrated circuit after a predetermined time delay, said preliminary latching logic being connected to the data bus of the mainframe to latch the data so that the latching circuit of said data catching and processing integrated circuit can catch the data, the latching logic of said data catching and processing integrated circuit being connected to said I/O signal decoding and processing circuit, said control signal catching and delay circuit, said preliminary latching logic, and the address bus of the mainframe, and sending the caught data to said parallel in serial out register array, said parallel in serial out register array sending the parallel input data to the serial in parallel out register array of said driver IC by means of serial output; the serial in parallel out register array of said driver IC sending the received data to the latching logic of said driver IC by means of parallel output, and the latching logic of said driver IC sending the caught data to said driver circuit, causing it to drive the respective LEDs of said LED array; said data catching and processing integrated circuit being to catch the major function signals of the mother board of the mainframe such as address bus signal, data bus signal, control bus signal, and regular I/O signals, then to send the signals to said driver IC for driving said LED array.