US4517671A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for operational analysis of computers
Assignee: Individual
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Filing: 1982-11-30
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Granted: 1985-05-14
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Expires: 2002-11-30
Abstract
Abstract An apparatus for operational analysis of computing devices which, when coupled to the address, data, and control buses of a computer, displays a representation of a selectable subgroup of the bus signals on a bit map display for each occurrence of a selectable condition. The bits of the least and most significant halves of the selected subgroup define the horizontal and vertical coordinates of a display pixel activated upon occurrence of the selectable condition. Selectable groups are address and data bus signals. An optional condition is specification of bit values of signals on the buses. Selectable control bus signal conditions are read or write and input/output or memory. The display is latched with the state of the selectable subgroup upon occurrence of the selectable conditions thereby remaining stable until the next occurence of the selectable conditions. Efficient adaptability to a variety of computer types is provided for by interchangeable personality interconnection modules that interconnect an optimized set of digital logic gates with the computer control bus signals and control condition selection switches. In a preferred embodiment the display is an array of Light Emitting Diodes which are energized by X and Y decoders in accordance with the group of signals selected to be displayed.
Inventors
- 👤 James D. Lewis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 01:15
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/221; G06F11/30; G06F11/32; G06F11/324; G06F11/325; G06F11/36; G06F11/362; G06F11/3636; G06F11/364; G06F11/3648
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
265 words
An apparatus for use in the operational analysis of a digital computer having control, address, and/or data signal buses, by displaying representations of selectable signals in response to the occurrence of selectable conditions comprising: (a) input buffering means, connectable to such a computer, for receiving a plurality of signals from signal buses within said computer and for outputting a plurality of buffered signals; (b) interchangeable personality definition means including digital logic means, connected to said input buffering means, for receiving buffered control bus signals and for outputting a control strobe signal, each such personality definition means adapting said apparatus for use with a particular computer; (c) first switch means, connected to said personality definition means, for selecting a state of said buffered control bus signals which defines a condition for output of said control strobe signal; (d) second switch means, including digital logic means, connected to said input buffering means, for selecting signals to be displayed from said address and/or data signal buses; (e) pattern recognizer means, including digital logic means, connected to said input buffering means, and said personality definition means for identifying states of address and data bus signals and outputting an enable strobe signal; (f) means connected to said pattern recognition means for defining digital values to be identified by said pattern recognition means; (g) storage means connected to said pattern recognizer means and said second switch means, for storing and outputting said signals selected to be displayed in response to said enable strobe and control strobe signals; and (h) display means connected to said storage means for displaying said selected signals.
Claim 2
Independent Claim
265 words
An apparatus for use in the operational analysis of a digital computer having control, address, and/or data signal buses, by displaying representations of selectable signals in response to the occurrence of selectable conditions comprising: (a) input buffering means, connectable to such a computer, for receiving a plurality of signals from signal buses within said computer and for outputting a plurality of buffered signals; (b) interchangeable personality definition means including digital logic means, connected to said input buffering means, for receiving buffered control bus signals and for outputting a control strobe signal, each such personality definition means adapting said apparatus for use with a particular computer; (c) first switch means, connected to said personality definition means, for selecting a state of said buffered control bus signals which defines a condition for output of said control strobe signal; (d) second switch means, including digital logic means, connected to said input buffering means, for selecting signals to be displayed from said address and/or data signal buses; (e) pattern recognizer means, including digital logic means, connected to said input buffering means, and said personality definition means for identifying states of address and data bus signals and outputting an enable strobe signal; (f) means connected to said pattern recognition means for defining digital values to be identified by said pattern recognition means; (g) storage means connected to said pattern recognizer means and said second switch means, for storing and outputting said signals selected to be displayed in response to said enable strobe and control strobe signals; and (h) display means connected to said storage means for displaying said selected signals.
Claim 3
Dependent Claim
36 words
The apparatus of claim 1 wherein said input buffering means further comprises digital device means for demultiplexing said control, address, and/or data signal buses whereby said apparatus is adapted for use with computers having multiplexed buses.
Claim 4
Dependent Claim
17 words
The apparatus of claim 1 wherein said display means is an array of light emitting diode pixels.
Claim 5
Dependent Claim
16 words
The apparatus of claim 3 wherein said pixels are arranged in a two dimensional 16×16 matrix.
Claim 6
Dependent Claim
35 words
The apparatus of claim 1 wherein said display means comprises digital to analog converters connected to said storage means and said display means is a cathode ray tube connected to said digital to analog converters.
Claim 7
Dependent Claim
54 words
The apparatus of claim 1 further comprising digital device means connected to said storage means and said display means for blanking said display means during a transition from the display of one state of the selected signals to the display of another state of the selected signals thereby eliminating erroneous activation of said display.
Claim 8
Dependent Claim
42 words
The apparatus of claim 1 wherein said storage means includes means for extending the duration of the on time that a state of said selected signal is displayed by said display means whereby the visibility of short duration signal events is increased.
Claim 9
Dependent Claim
23 words
The apparatus of claim 7 wherein said means for extending the duration of the time locks on displayed states of said selected signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-13 | 1988-11-12 | 1989-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-13 | 1992-11-12 | 1993-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-13 | 1996-11-12 | 1997-05-14 | $7700.00 | Window Closed / Lapsed |