US5644580A — Boundary-scan testable system and method

Claim 1

Independent Claim 100 words

A method of testing an integrated circuit that includes at least one output pin, core logic, an instruction register, a test access port (TAP) controller operable in a plurality of states, including an UPDATE-DR state and a SHIFT-DR state, and a Boundary-Scan cell coupled between said core logic and said output pin, said method comprising steps of: isolating said output pin from said core logic during said UPDATE-DR state when said instruction register contains an external test (EXTEST) instruction; and coupling said output pin to said core logic during said SHIFT-DR state when said instruction register contains said EXTEST instruction.

Claim 2

Independent Claim 100 words

A method of testing an integrated circuit that includes at least one output pin, core logic, an instruction register, a test access port (TAP) controller operable in a plurality of states, including an UPDATE-DR state and a SHIFT-DR state, and a Boundary-Scan cell coupled between said core logic and said output pin, said method comprising steps of: isolating said output pin from said core logic during said UPDATE-DR state when said instruction register contains an external test (EXTEST) instruction; and coupling said output pin to said core logic during said SHIFT-DR state when said instruction register contains said EXTEST instruction.

Claim 3

Dependent Claim 55 words

A method as claimed in claim 1 wherein: said TAP controller is additionally operable in CAPTURE-DR, SELECT-DR and RUN-TEST/IDLE states; and said method additionally comprises a step of isolating said output pin from said core logic during one or more of said CAPTURE-DR, SELECT-DR and RUN-TEST/IDLE states when said instruction register contains said EXTEST instruction.

Claim 4

Dependent Claim 57 words

A method as claimed in claim 1 wherein: said TAP controller is additionally operable in UPDATE-IR, EXIT1-DR, PAUSE-DR, AND EXIT2-DR states; and said method additionally comprises a step of coupling said output pin to said core logic during one or more of said UPDATE-IR, EXIT1-DR, PAUSE-DR, AND EXIT2-DR states when said instruction register contains said EXTEST instruction.

Claim 5

Dependent Claim 80 words

A method as claimed in claim 1 wherein said integrated circuit includes at least one input pin and a second Boundary-Scan cell coupled between said core logic and said input pin, said method additionally comprising steps of: isolating said input pin from said core logic during said UPDATE-DR state when said instruction register contains an internal test (INTEST) instruction; and coupling said input pin to said core logic during said SHIFT-DR state when said instruction register contains said INTEST instruction.

Claim 6

Dependent Claim 86 words

A method as claimed in claim 4 wherein said TAP controller is additionally operable in CAPTURE-DR, SELECT-DR, RUN-TEST/IDLE, UPDATE-IR, EXIT1-DR, PAUSE-DR, and EXIT2-DR states, said method additionally comprising steps of: isolating said input pin from said core logic during one or more of said CAPTURE-DR, SELECT-DR, and RUN-TEST/IDLE states when said instruction register contains said INTEST instruction; and coupling said input pin to said core logic during one or more of said UPDATE-IR, EXIT1-DR, PAUSE-DR, and EXIT2-DR states when said instruction register contains said INTEST instruction.

Claim 7

Independent Claim 81 words

A method of testing an integrated circuit that includes a Boundary-Scan test access port (TAP) controller operable in a plurality of states, including an UPDATE-DR state and a SHIFT-DR state, said method comprising steps of: loading a system action instruction into an instruction register; asserting a system action in accordance with said system action instruction during said UPDATE-DR state; and refraining from asserting said system action during said SHIFT-DR state while said system action instruction is loaded in said instruction register.

Claim 8

Independent Claim 81 words

A method of testing an integrated circuit that includes a Boundary-Scan test access port (TAP) controller operable in a plurality of states, including an UPDATE-DR state and a SHIFT-DR state, said method comprising steps of: loading a system action instruction into an instruction register; asserting a system action in accordance with said system action instruction during said UPDATE-DR state; and refraining from asserting said system action during said SHIFT-DR state while said system action instruction is loaded in said instruction register.

Claim 9

Dependent Claim 58 words

A method as claimed in claim 6 wherein said TAP controller is additionally operable in UPDATE-IR, EXIT1-DR, PAUSE-DR, AND EXIT2-DR states, and said method additionally comprises a step of refraining from asserting said system action during one or more of said UPDATE-IR, EXIT1-DR, PAUSE-DR, AND EXIT2-DR states while said system action instruction is loaded in said instruction register.

Claim 10

Dependent Claim 54 words

A method as claimed in claim 7 wherein said TAP controller is additionally operable in CAPTURE-DR, SELECT-DR, and RUN-TEST/IDLE states, and said method additionally comprises a step of asserting said system action during one or more of said CAPTURE-DR, SELECT-DR, and RUN-TEST/IDLE states while said system action instruction is loaded in said instruction register.

Claim 11

Independent Claim 118 words

A method for performing Boundary-Scan testing on an electronic system having at least one Boundary-Scan integrated circuit (BSIC) that includes at least one output pin, core logic, an instruction register, a test access port (TAP) controller operable in a plurality of states, including an UPDATE-DR state and a SHIFT-DR state, and a Boundary-Scan cell coupled between said core logic and said output pin, said method comprising steps of: loading an external test (EXTEST) instruction into said instruction register of said BSIC; isolating, in response to said loading step, said output pin from said core logic during said UPDATE-DR state; and coupling, in response to said loading step, said output pin to said core logic during said SHIFT-DR state.

Claim 12

Independent Claim 118 words

A method for performing Boundary-Scan testing on an electronic system having at least one Boundary-Scan integrated circuit (BSIC) that includes at least one output pin, core logic, an instruction register, a test access port (TAP) controller operable in a plurality of states, including an UPDATE-DR state and a SHIFT-DR state, and a Boundary-Scan cell coupled between said core logic and said output pin, said method comprising steps of: loading an external test (EXTEST) instruction into said instruction register of said BSIC; isolating, in response to said loading step, said output pin from said core logic during said UPDATE-DR state; and coupling, in response to said loading step, said output pin to said core logic during said SHIFT-DR state.

Claim 13

Dependent Claim 53 words

A method as claimed in claim 9 wherein said BSIC and a Boundary-Scan master couple to a data and control bus, and said method additionally comprises steps of: determining, at said Boundary-Scan master, when said isolating step will occur; and requesting control of said data and control bus prior to said isolating step.

Claim 14

Dependent Claim 117 words

A method as claimed in claim 10 wherein: said Boundary-Scan master generates a test mode select (TMS) signal which controls sequencing of said TAP controller through said states; said TAP controller of said BSIC is additionally operable in a PAUSE-DR state; said Boundary-Scan master generates a bus request signal and receives a bus granted signal; and said method additionally comprises, in response to said determining step, steps of: activating said bus request signal; controlling said TMS signal to hold said TAP controller of said BSIC in said Pause-DR state until said bus granted signal is received; and controlling said TMS signal so that said TAP controller exits said PAUSE-DR state after said bus granted signal is received.

Claim 15

Dependent Claim 52 words

A method as claimed in claim 11 additionally comprising, prior to said activating step, steps of: determining whether said data and control bus is already controlled by said Boundary-Scan master; and releasing control of said data and control bus when said data and control bus is already controlled by said Boundary-Scan master.

Claim 16

Dependent Claim 47 words

A method as claimed in claim 10 wherein said BSIC is a microprocessor, and said method additionally comprises a step of receiving programming data from said microprocessor at said Boundary-Scan master through said data and control bus, said programming data defining a Boundary-Scan test for said microprocessor.

Claim 17

Dependent Claim 53 words

A method as claimed in claim 9 wherein: said TAP controller is additionally operable in CAPTURE-DR, SELECT-DR, and RUN-TEST/IDLE states; and said method additionally comprises a step of isolating, in response to said loading step, said output pin from said core logic during one or more of said CAPTURE-DR, SELECT-DR, and RUN-TEST/IDLE states.

Claim 18

Dependent Claim 55 words

A method as claimed in claim 9 wherein said TAP controller is additionally operable in UPDATE-IR, EXIT1-DR, PAUSE-DR, AND EXIT2-DR states, and said method additionally comprises a step of coupling, in response to said loading step, said output pin to said core logic during one or more of said UPDATE-IR, EXIT1-DR, PAUSE-DR, AND EXIT2-DR states.

Claim 19

Dependent Claim 64 words

A Boundary-Scan master coupled to a data and control bus, said Boundary-Scan master including: means for determining when an external test (EXTEST) instruction will assert a system action; and means for requesting control of said data and control bus prior to said assertion of said system action in response to signals from said means for determining, said determining means coupled to said requesting means.

Claim 20

Dependent Claim 64 words

A Boundary-Scan master coupled to a data and control bus, said Boundary-Scan master including: means for determining when an external test (EXTEST) instruction will assert a system action; and means for requesting control of said data and control bus prior to said assertion of said system action in response to signals from said means for determining, said determining means coupled to said requesting means.

Claim 21

Dependent Claim 93 words

A Boundary-Scan master as claimed in claim 16 wherein: said Boundary-Scan master generates a test mode select (TMS) signal which controls Boundary-Scan testing of an integrated circuit (IC) having an instruction register and a test access port (TAP) controller for operating in a plurality of states, including an EXIT1-DR state; and said determining means additionally includes means for identifying when said EXTEST instruction is loaded in said instruction register of said IC and said TAP controller has entered said EXIT1-DR state, said identifying means coupled to said determining means and said requesting means.

Claim 22

Dependent Claim 124 words

A Boundary-Scan master as claimed in claim 16 wherein: said Boundary-Scan master generates a test mode select (TMS) signal for controlling Boundary-Scan testing of an integrated circuit (IC) having an instruction register and a test access port (TAP) controller for operating in a plurality of states, including a PAUSE-DR state; said Boundary-Scan master generates a bus request signal and receives a bus granted signal; and said Boundary-Scan master additionally comprises, in response to said determining means, means for: activating said bus request signal; controlling said TMS signal to hold said TAP controller in said PAUSE-DR state until said bus granted signal is received; and controlling said TMS signal so that said TAP controller exits said PAUSE-DR state after said bus granted signal is received.

Claim 23

Dependent Claim 55 words

A Boundary-Scan master as claimed in claim 18 additionally comprising means for, prior to activating by said activating means: determining whether said data and control bus is already controlled by said Boundary-Scan master; and releasing control of said data and control bus when said data and control bus is already controlled by said Boundary-Scan master.

Claim 24

Dependent Claim 125 words

A Boundary-Scan master as claimed in claim 16 wherein: said Boundary-Scan master generates a test mode select (TMS) signal for controlling Boundary-Scan testing of an integrated circuit (IC) having an instruction register and a test access port (TAP) controller for operating in a plurality of states, including a PAUSE-IR state; said Boundary-Scan master generates a bus request signal and receives a bus granted signal; and said Boundary-Scan master additionally comprises means, operating in response to said determining means, for: activating said bus request signal; controlling said TMS signal to hold said TAP controller in said PAUSE-IR state until said bus granted signal is received; and regulating said TMS signal so that said TAP controller exits said PAUSE-IR state after said bus granted signal is received.

Claim 25

Dependent Claim 98 words

A Boundary-Scan master as claimed in claim 20 wherein said TAP controller is additionally for operating in an EXIT1-DR state, and said Boundary-Scan master additionally comprises, coupled to and responsive to said regulating means, means for: identifying when said EXTEST instruction is loaded in said instruction register and said TAP controller has entered said EXIT1-DR state; determining, in response to said identifying means, whether said data and control bus is being controlled by said Boundary-Scan master; and releasing control of said data and control bus when said data and control bus is being controlled by said Boundary-Scan master.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2000-06-30	2000-12-30	2001-07-01	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2004-06-30	2004-12-30	2005-07-01	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2008-06-30	2008-12-30	2009-07-01	$7700.00	Window Closed / Lapsed

Boundary-scan testable system and method

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