Patent US5644541A successfully refreshed from Google Patents.
US5644541A
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US
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Memory substitution system and method for correcting partially defective memories
Assignee: Individual
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Filing: 1995-11-03
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Granted: 1997-07-01
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Expires: 2015-11-03
Abstract
Abstract A memory system comprises a plurality of semiconductor memories with some bad bits, a substitution memory and a mapping logic to redirect external memory accesses to bad-bit locations in the semiconductor memories to good storage cells within the substitution memory.
Inventors
- 👤 Philip K. Siu
- 👤 Lawrence K. Lo
- 👤 Hing S. Tong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:55
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/80
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
187 words
A memory repair integrated circuit (IC), comprising on a single semiconductor device: a bad address record (BAR) with an input connected to receive data access requests by system addresses and a plurality of outputs for selecting one of several off-chip dynamic random access memories (DRAM's) or an on-chip memory array to respond to for each particular data access request according to a prerecorded list of defective bits in said off-chip DRAM's; an X-address latch and decoder connected to receive said system addresses from the BAR and connected to a first plurality of rows of memory elements in said memory array; a Y-address latch and decoder connected to receive said system addresses from the BAR and connected to a second plurality of rows of memory elements in said memory array; a sense amplifier connected to receive data from said first and second plurality of rows of memory in said memory array; and a data buffer connected to receive data from the sense amplifier and to provide said received data to a databus connected to said DRAM's, and connected to write data to said memory array from said databus.
Claim 2
Dependent Claim
187 words
A memory repair integrated circuit (IC), comprising on a single semiconductor device: a bad address record (BAR) with an input connected to receive data access requests by system addresses and a plurality of outputs for selecting one of several off-chip dynamic random access memories (DRAM's) or an on-chip memory array to respond to for each particular data access request according to a prerecorded list of defective bits in said off-chip DRAM's; an X-address latch and decoder connected to receive said system addresses from the BAR and connected to a first plurality of rows of memory elements in said memory array; a Y-address latch and decoder connected to receive said system addresses from the BAR and connected to a second plurality of rows of memory elements in said memory array; a sense amplifier connected to receive data from said first and second plurality of rows of memory in said memory array; and a data buffer connected to receive data from the sense amplifier and to provide said received data to a databus connected to said DRAM's, and connected to write data to said memory array from said databus.
Claim 3
Dependent Claim
51 words
The IC of claim 1, wherein: the X-address latch and decoder, and the Y-address latch and decoder comprise a set of programmable fuses each individually connected to a plurality of transistors controlled by said system addresses and having a word-line and a y-select output to control access to said memory array.
Claim 4
Dependent Claim
45 words
The IC of claim 1, wherein: the X-address latch and decoder, and the Y-address latch and decoder comprise a plurality of programmable voltage threshold transistors controlled by said system addresses and having a word-line and a y-select output to control access to said memory array.
Claim 5
Independent Claim
191 words
A system memory module, comprising: a plurality of possibly-defective memory devices connected to a data bus and each having at least one bad memory bit cell that is externally accessible; a substitution memory connected to said data bus; a timing and control unit having an input to receive an external memory access signal, an address bus output connected to the possibly-defective memory devices, and a latched-address bus output connected to the substitution memory; and a comparator logic and mapping memory connected to receive said external memory access signals and having a memory substitution control output connected to the timing and address comparator unit for selecting whether the substitution memory or the plurality of possibly-defective memory devices can respond to an external memory access, and having programming means for selecting, on an address-by-address basis, which of a plurality of system memory module address inputs cause the substitution memory to respond instead of any of the possibly-defective memory devices, wherein a memory access cycle to an address within the possibly-defective memory devices actually having a defective memory bit is programmably redirected to access the substitution memory for both read and write memory cycles.
Claim 6
Independent Claim
191 words
A system memory module, comprising: a plurality of possibly-defective memory devices connected to a data bus and each having at least one bad memory bit cell that is externally accessible; a substitution memory connected to said data bus; a timing and control unit having an input to receive an external memory access signal, an address bus output connected to the possibly-defective memory devices, and a latched-address bus output connected to the substitution memory; and a comparator logic and mapping memory connected to receive said external memory access signals and having a memory substitution control output connected to the timing and address comparator unit for selecting whether the substitution memory or the plurality of possibly-defective memory devices can respond to an external memory access, and having programming means for selecting, on an address-by-address basis, which of a plurality of system memory module address inputs cause the substitution memory to respond instead of any of the possibly-defective memory devices, wherein a memory access cycle to an address within the possibly-defective memory devices actually having a defective memory bit is programmably redirected to access the substitution memory for both read and write memory cycles.
Claim 7
Dependent Claim
84 words
The module of claim 4, wherein: the plurality of possibly-defective memory devices comprises dynamic random access memories with partially defective memory storage; the substitution memory comprises a static random access memory having an access time faster than that of the plurality of possibly-defective memory devices; and the comparator logic and mapping memory comprises an electrically erasable and programmable read only memory (EEPROM) with external connections for programming of mapping addresses corresponding to addresses within said defective memory storage by an external module test unit.
Claim 8
Dependent Claim
173 words
The module of claim 4, wherein: the plurality of possibly-defective memory devices comprises a plurality of dynamic random access memory (DRAM) integrated circuit devices connected to a data bus and each having at least one bad memory bit cell that is externally accessible; the substitution memory comprises a static random access memory (SRAM) connected to said data bus; the comparator logic and mapping memory comprises an electrically erasable and programmable read only memory (EEPROM) connected to receive said external memory access signals and having a substitution control output connected to the timing and control unit to cause either the DRAM to be enabled or the SRAM to be enabled, and having programming means for selecting on an address-by-address basis which of a plurality of system memory module address inputs cause said substitution control output to enable the SRAM instead of the DRAM, wherein a memory access cycle to an address within the DRAM integrated circuit devices having a defective memory bit is redirected to the SRAM for both read and write memory accesses.
Claim 9
Dependent Claim
43 words
The module of claim 4, wherein: the substitution memory, the timing and control unit and the comparator logic and control unit are all integrated on a single integrated circuit with connections provided for externally connected ones of the plurality of possibly-defective memory devices.
Claim 10
Dependent Claim
53 words
The module of claim 4, wherein: the substitution memory, the timing and control unit, the comparator logic and control unit, and the plurality of possibly-defective memory devices are all constructed on one single-in-line memory module (SIMM) with external connections provided for interfacing through printed circuit board memory module connectors to a personal computer.
Claim 11
Dependent Claim
143 words
A memory module test and programming unit for programming a discrete and separate programmable read only memory (PROM) with which memory locations in a combination of discrete and separate dynamic random access memories (DRAM) and discrete and separate static random access memories (SRAM) in a single memory module are to respond with the SRAM rather than with the DRAM due to non-programmable or non-readable memory locations within said DRAM, comprising: addressing means for accessing a plurality of memory addresses associated with a memory module and for determining which memory locations have defects; and programming means for registering the addresses of non-programmable or non-readable memory locations in a programmable read only memory (PROM) connected between a DRAM and an SRAM for preferring the SRAM over the DRAM at each of said non-programmable or non-readable memory locations during an external access of said memory module.
Claim 12
Dependent Claim
143 words
A memory module test and programming unit for programming a discrete and separate programmable read only memory (PROM) with which memory locations in a combination of discrete and separate dynamic random access memories (DRAM) and discrete and separate static random access memories (SRAM) in a single memory module are to respond with the SRAM rather than with the DRAM due to non-programmable or non-readable memory locations within said DRAM, comprising: addressing means for accessing a plurality of memory addresses associated with a memory module and for determining which memory locations have defects; and programming means for registering the addresses of non-programmable or non-readable memory locations in a programmable read only memory (PROM) connected between a DRAM and an SRAM for preferring the SRAM over the DRAM at each of said non-programmable or non-readable memory locations during an external access of said memory module.
Claim 13
Dependent Claim
73 words
The unit of claim 9, further comprising: means for mapping said non-programmable or non-readable memory location addresses; wherein, said non-programmable or non-readable memory location addresses are grouped and then mapped according to a row position of each particular address in a memory array; and wherein, a pre-existing row and column organization of the memory cells is mimicked during read operations in order to preserve the access timing of page-mode types of said DRAMs.
Claim 14
Independent Claim
111 words
A method of programming a memory module comprised of a combination of discrete and separate dynamic random access memory (DRAM) and static random access memory (SRAM) to respond with SRAM rather than with DRAM for memory locations in said DRAM with non-programmable or non-readable memory bits, comprising the steps of: writing a test pattern to said DRAM at a first address; reading back data from said DRAM at said first address; comparing said data read with said data written; and programming a means for permanently selecting said SRAM to respond instead of said DRAM at said first address if the step of comparing indicates a faulty memory cell within said DRAM.
Claim 15
Independent Claim
111 words
A method of programming a memory module comprised of a combination of discrete and separate dynamic random access memory (DRAM) and static random access memory (SRAM) to respond with SRAM rather than with DRAM for memory locations in said DRAM with non-programmable or non-readable memory bits, comprising the steps of: writing a test pattern to said DRAM at a first address; reading back data from said DRAM at said first address; comparing said data read with said data written; and programming a means for permanently selecting said SRAM to respond instead of said DRAM at said first address if the step of comparing indicates a faulty memory cell within said DRAM.
Claim 16
Dependent Claim
61 words
The method of claim 11, further comprising the subsequent step of: mapping any non-programmable or non-readable memory location addresses that are detected in the step of comparing in groups according to the particular addresses' row position in said memory array to a row and column organization of memory cells, wherein the access timing of page-mode types of said DRAMs is preserved.
Claim 17
Independent Claim
110 words
A method for a memory module to respond to a memory access where said memory module comprises a combination of discrete and separate dynamic random access memory (DRAM) and static random access memory (SRAM) memory that provides for a response by said SRAM rather than by said DRAM for memory locations in said DRAM with non-programmable or non-readable bits, comprising the steps of: inputting an address to said memory module for a memory access cycle; comparing said address to a list of addresses previously identified as having non-programmable or non-readable bits in said DRAM; and substituting-in a location in said SRAM for each previously identified non-programmable or non-readable DRAM address.
Claim 18
Independent Claim
110 words
A method for a memory module to respond to a memory access where said memory module comprises a combination of discrete and separate dynamic random access memory (DRAM) and static random access memory (SRAM) memory that provides for a response by said SRAM rather than by said DRAM for memory locations in said DRAM with non-programmable or non-readable bits, comprising the steps of: inputting an address to said memory module for a memory access cycle; comparing said address to a list of addresses previously identified as having non-programmable or non-readable bits in said DRAM; and substituting-in a location in said SRAM for each previously identified non-programmable or non-readable DRAM address.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-30 | 2000-12-30 | 2001-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-30 | 2004-12-30 | 2005-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-30 | 2008-12-30 | 2009-07-01 | $7700.00 | Window Closed / Lapsed |