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US5644252A
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US
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Driver for interfacing integrated circuits to transmission lines
Assignee: Renesas Electronics Corp
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Filing: 1996-03-11
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Granted: 1997-07-01
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Expires: 2016-03-11
Abstract
Abstract In order to effectively interface a plurality of integrated circuits to a bus, an improved driver is disclosed. The driver includes an inverter provided between a power source and a ground level, and an output transistor whose gate is coupled to an output of the inverter and whose source-drain path is coupled between an output of the driver and the second power source. A feedback path is coupled between the output of the driver and the output of the inverter. The feedback path includes first and second transistors coupled in series. The first transistor has its gate coupled to an input of the inverter, while the second transistor has its gate coupled to the output of the inverter via delay means. The driver is characterized by an impedance controller which is provided between the output of the inverter and the second power source. The impedance controller stepwisely adjusts impedance of the output transistor when an input signal to the inverter changes from a low logic level to a high logic level. As an alternative to or in combination of the impedance controller, another impedance controller is provided which is provided in parallel with the second transistor and which stepwisely adjusts the impedance of the output transistor when the input signal to the inverter changes from the low logic level to the high logic level.
Inventors
- 👤 Seiichi Watarai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 19:56
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/0264; H04L25/0278; G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072; H03; H03K; H03K17/00; H03K17/16; H03K17/161; H03K17/165; H03K17/166; H03K17/167; H04L25/028; H04L25/03; H04L25/03828; H04L25/03834
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
171 words
A driver for interfacing a plurality of integrated circuits to a bus, said driver comprising: an inverter (62, 64) provided between first and second power sources (66, 68); an output transistor (43) whose gate is coupled to an output of said inverter and whose source-drain path is coupled between an output (38a) of said driver and said second power source; a feedback path coupled between the output of said driver and the output of said inverter, said feedback path including first and second transistors (56, 54) coupled in series, said first transistor (56) having a gate thereof coupled to an input of said inverter, said second transistor (54) having a gate thereof coupled to the output of said inverter via delay means; characterized in that an impedance controller (72, 74) is provided between the output of said inverter and said second power source, said impedance controller stepwisely adjusting impedance of said output transistor when an input signal to said inverter changes from a low logic level to a high logic level.
Claim 2
Dependent Claim
171 words
A driver for interfacing a plurality of integrated circuits to a bus, said driver comprising: an inverter (62, 64) provided between first and second power sources (66, 68); an output transistor (43) whose gate is coupled to an output of said inverter and whose source-drain path is coupled between an output (38a) of said driver and said second power source; a feedback path coupled between the output of said driver and the output of said inverter, said feedback path including first and second transistors (56, 54) coupled in series, said first transistor (56) having a gate thereof coupled to an input of said inverter, said second transistor (54) having a gate thereof coupled to the output of said inverter via delay means; characterized in that an impedance controller (72, 74) is provided between the output of said inverter and said second power source, said impedance controller stepwisely adjusting impedance of said output transistor when an input signal to said inverter changes from a low logic level to a high logic level.
Claim 3
Dependent Claim
63 words
A driver as claimed in claim 1, wherein said impedance controller includes a plurality of transistors (72, 74) coupled in parallel with each other, said plurality of transistors being non-conductive while said input signal assumes the low logic level and being successively rendered conductive in response to a change of said input signal from the low logic level to the high logic level.
Claim 4
Dependent Claim
42 words
A driver as claimed in claim 2, wherein said delay means including a plurality of inverters (70a-70f) coupled in series, said plurality of transistors of said impedance controller having gates thereof coupled to said inverters such as to be successively rendered conductive.
Claim 5
Dependent Claim
52 words
A driver as claimed in claim 1, further comprising another impedance controller (82a, 82b) which is provided in parallel with said second transistor, said another impedance controller stepwisely adjusting impedance of said output transistor when an input signal to said inverter changes from a low logic level to a high logic level.
Claim 6
Dependent Claim
64 words
A driver as claimed in claim 4, wherein said another impedance controller includes a plurality of transistors (82a, 82b) coupled in parallel with each other, said plurality of transistors being non-conductive while said input signal assumes the low logic level and being successively rendered conductive in response to a change of said input signal from the low logic level to the high logic level.
Claim 7
Dependent Claim
43 words
A driver as claimed in claim 5, wherein said delay means including a plurality of inverters (70a-70f) coupled in series, said plurality of transistors of said another impedance controller having gates thereof coupled to said inverters such as to be successively rendered conductive.
Claim 8
Dependent Claim
63 words
A driver as claimed in claim 5, wherein said impedance controller includes a plurality of transistors (82a, 82b) coupled in parallel with each other, said plurality of transistors being non-conductive while said input signal assumes the low logic level and being successively rendered conductive in response to a change of said input signal from the low logic level to the high logic level.
Claim 9
Dependent Claim
42 words
A driver as claimed in claim 7, wherein said delay means including a plurality of inverters (70a-70f) coupled in series, said plurality of transistors of said impedance controller having gates thereof coupled to said inverters such as to be successively rendered conductive.
Claim 10
Dependent Claim
166 words
A driver for interfacing a plurality of integrated circuits to a bus, said driver comprising: an inverter (62, 64) provided between first and second power sources (66, 68); an output transistor (43) whose gate is coupled to an output of said inverter and whose source-drain path is coupled between an output (38a) of said driver and said second power source; a feedback path coupled between the output of said driver and the output of said inverter, said feedback path including first and second transistors (56, 54) coupled in series, said first transistor (56) having a gate thereof coupled to an input of said inverter, said second transistor (54) having a gate thereof coupled to the output of said inverter via delay means; characterized in that an impedance controller (82a, 82b) is provided in parallel with said second transistor, said impedance controller adjusting stepwisely impedance of said output transistor when an input signal to said inverter changes from a low logic level to a high logic level.
Claim 11
Dependent Claim
166 words
A driver for interfacing a plurality of integrated circuits to a bus, said driver comprising: an inverter (62, 64) provided between first and second power sources (66, 68); an output transistor (43) whose gate is coupled to an output of said inverter and whose source-drain path is coupled between an output (38a) of said driver and said second power source; a feedback path coupled between the output of said driver and the output of said inverter, said feedback path including first and second transistors (56, 54) coupled in series, said first transistor (56) having a gate thereof coupled to an input of said inverter, said second transistor (54) having a gate thereof coupled to the output of said inverter via delay means; characterized in that an impedance controller (82a, 82b) is provided in parallel with said second transistor, said impedance controller adjusting stepwisely impedance of said output transistor when an input signal to said inverter changes from a low logic level to a high logic level.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-30 | 2000-12-30 | 2001-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-30 | 2004-12-30 | 2005-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-30 | 2008-12-30 | 2009-07-01 | $7700.00 | Window Closed / Lapsed |