US5539336A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed driver circuit with improved off transition feedback
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1995-05-01
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Granted: 1996-07-23
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Expires: 2015-05-01
Abstract
Abstract A driver circuit has a single feedback transistor in the driver transistor well to provide a momentary feedback from source to gate and maintain conductance of the driver transistor during turnoff of the driver transistor and thus reduce ringing oscillation at the transistor source output. An enable/disable signal is applied to control conduction circuitry and the driver transistor and force the output to a high impedance state when the circuit is disabled. Clocked operation of the driver circuit is provided with circuitry merged with a latch. A terminal for receiving a global i dd test signal controls circuitry removing power to the driver circuit and applying a ground potential to the driver output in response to the global i dd test signal.
Inventors
- 👤 Trung Nguyen
- 👤 George Shing
- 👤 Luong Hung
- 👤 Gary H. Cheung
- 👤 Elias Lozano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:04
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361; H03K17/00; H03K17/16; H03K17/161; H03K17/165; H03K17/166
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
131 words
A driver circuit comprising a driver transistor having a source, a gate, and a drain, a feedback transistor having a source, a gate, and a drain, said source being connected to said source of said driver transistor and said drain being connected to said gate of said driver transistor, an input terminal for receiving input signals, an output terminal connected to said source of said driver transistor and to said source of said feedback transistor, first conduction means for connecting said input terminal to said gate of said driver transistor, and second conduction means including delay circuitry for connecting said input terminal to said gate of said feedback transistor whereby a pulse transition on said input terminal turns-off said driver transistor, said turn-off being-delayed by momentary conduction of said feedback transistor.
Claim 2
Dependent Claim
131 words
A driver circuit comprising a driver transistor having a source, a gate, and a drain, a feedback transistor having a source, a gate, and a drain, said source being connected to said source of said driver transistor and said drain being connected to said gate of said driver transistor, an input terminal for receiving input signals, an output terminal connected to said source of said driver transistor and to said source of said feedback transistor, first conduction means for connecting said input terminal to said gate of said driver transistor, and second conduction means including delay circuitry for connecting said input terminal to said gate of said feedback transistor whereby a pulse transition on said input terminal turns-off said driver transistor, said turn-off being-delayed by momentary conduction of said feedback transistor.
Claim 3
Dependent Claim
40 words
The driver circuit as defined by claim 1 wherein said driver circuit is part of an integrated circuit fabricated in a semiconductor body, said driver transistor and said feedback transistor being fabricated in a doped well in said semiconductor body.
Claim 4
Dependent Claim
56 words
The driver circuit as defined by claim 2 wherein said first conduction means includes a first pass gate serially connected with a first inverter, and said second conduction means includes a second pass gate and a plurality of serially connected inverters connecting an output of said first inverter to bias terminals of said second pass gate.
Claim 5
Dependent Claim
78 words
The driver circuit as defined by claim 3 and further including an enable terminal for receiving a circuit enable/disable signal, third conduction means connecting said enable terminal to said first pass gate for controlling conduction of said first pass gate, and fourth conduction means responsive to said enable/disable signal for applying a bias voltage through said first inverter to said gate terminal of said driver transistor for rendering said driver transistor non-conductive when said driver circuit is disabled.
Claim 6
Dependent Claim
58 words
The driver circuit as defined by claim 4 and further including a clock input terminal for applying clock signals to activate said driver circuit, logic means receiving said enable/disable signal and said clock signals as inputs and providing clock signals as an output when said circuit is enabled, said clock signals controlling conduction of said first pass gate.
Claim 7
Dependent Claim
78 words
The driver circuit as defined by claim 2 and further including an enable terminal for receiving a circuit enable/disable signal, third conduction means connecting said enable terminal to said first conduction means for controlling conduction of said first conduction means, and fourth conduction means responsive to said enable/disable signal for applying a bias voltage through said first inverter to said gate terminal of said driver transistor for rendering said driver transistor non-conductive when said driver circuit is disabled.
Claim 8
Dependent Claim
58 words
The driver circuit as defined by claim 6 and further including a clock input terminal for applying clock signals to activate said driver circuit, logic means receiving said enable/disable signal and said clock signals as inputs and providing clock signals as an output when said circuit is enabled, said clock signals controlling conduction of said first conduction means.
Claim 9
Dependent Claim
61 words
The driver circuit as defined by claim 7 and further including an i dd test terminal for receiving a global signal to shut off all d.c. current for i dd testing, and circuit means connected with said i dd test terminal for disconnecting power to said driver circuit and for applying a ground potential to said source of said driver transistor.
Claim 10
Dependent Claim
61 words
The driver circuit as defined by claim 2 and further including an i dd test terminal for receiving a global signal to shut off all d.c. current for i dd testing and circuit means connected with said i dd test terminal for disconnecting power to said driver circuit and for applying a ground potential to said source of said driver transistor.
Claim 11
Dependent Claim
134 words
A driver circuit comprising a driver transistor having a source, a gate, and a drain, a feedback transistor having a source, a gate, and a drain, said source being connected to said source of said driver transistor and said drain being connected to said gate of said driver transistor, an input terminal for receiving input signals, an output terminal connected to said source of said driver transistor and to said source of said feedback transistor, a first conduction path for connecting said input terminal to said gate of said driver transistor, and a second conduction path including delay circuitry for connecting said input terminal to said gate of said feedback transistor whereby a pulse transition on said input terminal turns-off said driver transistor, said turn-off being delayed by momentary conduction of said feedback transistor.
Claim 12
Dependent Claim
134 words
A driver circuit comprising a driver transistor having a source, a gate, and a drain, a feedback transistor having a source, a gate, and a drain, said source being connected to said source of said driver transistor and said drain being connected to said gate of said driver transistor, an input terminal for receiving input signals, an output terminal connected to said source of said driver transistor and to said source of said feedback transistor, a first conduction path for connecting said input terminal to said gate of said driver transistor, and a second conduction path including delay circuitry for connecting said input terminal to said gate of said feedback transistor whereby a pulse transition on said input terminal turns-off said driver transistor, said turn-off being delayed by momentary conduction of said feedback transistor.
Claim 13
Dependent Claim
40 words
The driver circuit as defined by claim 10 wherein said driver circuit is part of an integrated circuit fabricated in a semiconductor body, said driver transistor and said feedback transistor being fabricated in a doped well in said semiconductor body.
Claim 14
Dependent Claim
56 words
The driver circuit as defined by claim 11 wherein said first conduction path includes a first pass gate serially connected with a first inverter, and said second conduction path includes a second pass gate and a plurality of serially connected inverters connecting an output of said first inverter to bias terminals of said second pass gate.
Claim 15
Dependent Claim
80 words
The driver circuit as defined by claim 12 and further including an enable terminal for receiving a circuit enable/disable signal, a third conduction path connecting said enable terminal to said first pass gate for controlling conduction of said first pass gate, and a fourth conduction path responsive to said enable/disable signal for applying a bias voltage through said first inverter to said gate terminal of said driver transistor for rendering said driver transistor non-conductive when said driver circuit is disabled.
Claim 16
Dependent Claim
58 words
The driver circuit as defined by claim 13 and further including a clock input terminal for applying clock signals to activate said driver circuit, logic circuitry receiving said enable/disable signal and said clock signals as inputs and providing clock signals as an output when said circuit is enabled, said clock signals controlling conduction of said first pass gate.
Claim 17
Dependent Claim
164 words
In a driver circuit including a driver transistor having a source, a gate, and a drain formed in a doped well in a semiconductor body, a method of suppressing ringing when the driver transistor turns off comprising the step of a) providing a feedback transistor in said well, said feedback transistor having a source, a gate, and a drain, said source being connected to said source of said driver transistor and said drain being connected to said gate of said driver transistor, an output terminal connected to said source of said driver transistor and to said source of said feedback transistor, b) providing a first conduction path for connecting an input terminal to said gate of said driver transistor, and c) providing a second conduction path including delay circuitry for connecting said input terminal to said gate of said feedback transistor whereby a pulse transition on said input terminal turns-off said driver transistor, said turn-off being delayed by momentary conduction of said feedback transistor.
Claim 18
Dependent Claim
164 words
In a driver circuit including a driver transistor having a source, a gate, and a drain formed in a doped well in a semiconductor body, a method of suppressing ringing when the driver transistor turns off comprising the step of a) providing a feedback transistor in said well, said feedback transistor having a source, a gate, and a drain, said source being connected to said source of said driver transistor and said drain being connected to said gate of said driver transistor, an output terminal connected to said source of said driver transistor and to said source of said feedback transistor, b) providing a first conduction path for connecting an input terminal to said gate of said driver transistor, and c) providing a second conduction path including delay circuitry for connecting said input terminal to said gate of said feedback transistor whereby a pulse transition on said input terminal turns-off said driver transistor, said turn-off being delayed by momentary conduction of said feedback transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-23 | 2000-01-22 | 2000-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-23 | 2004-01-22 | 2004-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-23 | 2008-01-22 | 2008-07-23 | $7700.00 | Window Closed / Lapsed |