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US5639682A
Expired / Lapsed
US
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Method of forming a semiconductor device using a self-aligned contact
Assignee: Samsung Electronics Co Ltd
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Filing: 1995-11-03
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Granted: 1997-06-17
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Expires: 2015-11-03
Abstract
Abstract A semiconductor device using a self-aligned contact and a method for manufacturing the same is disclosed. A gate electrode having a first spacer formed on the sidewalls thereof is formed on a semiconductor substrate. Active regions which are spaced apart from each other by the gate electrode are formed in the semiconductor substrate. A bitline having a second spacer formed on the sidewalls thereof is formed on the gate electrode and the active regions. A self-aligned contact is formed on the active regions and a first pad electrode connected with the active region through the contact is formed between the bitlines. A bitline contact is formed on the bitline, and second and third pad electrodes, which are respectively connected with the bitline and the first pad electrode through the bitline contact, are formed on the bitline. Thus, the alignment tolerances of the bitline contact and the storage-node contact are maximized, so that a reliable semiconductor device can be realized.
Inventors
- 👤 Hyun-cheol Choe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:57
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/48; H10B12/482; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
210 words
A method for manufacturing a semiconductor memory device comprising the steps of: forming gate electrodes on a semiconductor substrate; forming active regions in said semiconductor substrate, respective pairs of active regions being spaced apart from each other one said gate electrode; forming a first insulating film on the resultant structure having said active regions; forming bitlines on said first insulating film; forming a second insulating film on said bitlines; forming a first spacer and a second spacer composed of said first insulating film and second insulating film, respectively, on the sidewalls of said gate electrodes and said bitlines, respectively, and, simultaneously forming a self-aligned contact over said active regions; depositing a first conductive material on the resultant structure wherein said contact is formed, and etching said first conductive material, to thereby form a first pad electrode which is electrically connected with said active region between said bitlines; forming a bitline contact on said bitlines; and depositing a second conductive material on the resultant structure wherein said bitline contact is formed, and patterning said second conductive material by a lithography process to thereby form a second pad electrode connected with said bitline via the bitline contact and a third pad electrode connected with said first pad electrode via the bitline contact.
Claim 2
Independent Claim
210 words
A method for manufacturing a semiconductor memory device comprising the steps of: forming gate electrodes on a semiconductor substrate; forming active regions in said semiconductor substrate, respective pairs of active regions being spaced apart from each other one said gate electrode; forming a first insulating film on the resultant structure having said active regions; forming bitlines on said first insulating film; forming a second insulating film on said bitlines; forming a first spacer and a second spacer composed of said first insulating film and second insulating film, respectively, on the sidewalls of said gate electrodes and said bitlines, respectively, and, simultaneously forming a self-aligned contact over said active regions; depositing a first conductive material on the resultant structure wherein said contact is formed, and etching said first conductive material, to thereby form a first pad electrode which is electrically connected with said active region between said bitlines; forming a bitline contact on said bitlines; and depositing a second conductive material on the resultant structure wherein said bitline contact is formed, and patterning said second conductive material by a lithography process to thereby form a second pad electrode connected with said bitline via the bitline contact and a third pad electrode connected with said first pad electrode via the bitline contact.
Claim 3
Dependent Claim
34 words
A method for manufacturing a semiconductor device as claimed in claim 1, wherein said bitlines and said gate electrodes are used as an etch-blocking layer in said step of forming said first pad electrode.
Claim 4
Dependent Claim
73 words
A method for manufacturing a semiconductor device as claimed in claim 1, wherein in said step of forming said first and second spacers on the sidewalls of said gate electrodes and said bitlines, said first insulating film is also etched when said second spacer is formed on the sidewalls of said bitlines by anisotropically etching said second insulating film, so that said first spacers are formed on the sidewalls of said gate electrodes.
Claim 5
Dependent Claim
35 words
A method for manufacturing a semiconductor device as claimed in claim 1, wherein the layout size of said bitline contact is larger than that of said active region which will be connected with said bitline.
Claim 6
Dependent Claim
20 words
A method for manufacturing a semiconductor device as claimed in claim 1, wherein said bitlines lie along substantially one direction.
Claim 7
Dependent Claim
30 words
A method for manufacturing a semiconductor device as claimed in claim 1, wherein said first conductive material is formed to a thickness equal to the distance between adjacent said bitlines.
Claim 8
Dependent Claim
77 words
A method for manufacturing a semiconductor device as claimed in claim 1, wherein after said step of forming said second and third pad electrodes, the method further comprises the steps of: forming a third insulating film on the resultant structure; partially etching said third insulating film, to thereby form a storage-node contact on said third pad electrode; and forming a capacitor storage node connected with said third pad electrode through said storage-node contact on the resultant structure.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-16 | 2000-12-16 | 2001-06-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-16 | 2004-12-16 | 2005-06-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-16 | 2008-12-16 | 2009-06-17 | $7700.00 | Window Closed / Lapsed |