US5634075A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Backward compatibility for plug and play systems
Assignee: Cirrus Logic Inc
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Filing: 1995-01-11
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Granted: 1997-05-27
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Expires: 2015-01-11
Abstract
Abstract A device for use in a computer system, particularly a personal computer (PC) which provides compatibility for a proposed ISA plug and play (PNP) standard. The device of the present invention is also backward compatible with non-PNP (legacy) PCs. Upon power-up, a device may initialize using default traditional or specification (ISA) values for I/O address, IRQ and DMA channels. If PNP activity by the host PC is detected by the device, the device is disabled, and awaits activation and I/O address, IRQ and DMA channel assignments from a host PC. If no PNP activity by a host PC is detected, the device continues to operate using default traditional or specification (ISA) I/O address, IRQ and DMA channels. The device of the present invention may be installed in PNP or legacy type PCs without reconfiguring hardware (e.g., DIP switches, jumpers or the like) in the device or installing new firmware, operating system, or applications software in a host PC.
Inventors
- 👤 Stephen A. Smith
- 👤 Suhas A. Shetty
- 👤 Daniel G. Bezzant
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:16
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/44; G06F9/4401; G06F9/4411; G06F12/00; G06F12/02; G06F12/06; G06F12/0646
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
280 words
A backward compatible plug and play device for adaptive use with a computer of either a PNP or a legacy non-PNP type having system data and address busses, said device being coupled to said computer system data and address busses, said device comprising: first storage means, coupled to said computer system data bus, for storing an I/O address for the device, wherein said first storage means outputs a default I/O address upon power-up; a DMA channel register, coupled to said computer system data bus, for storing a DMA channel value for the device, wherein said DMA channel register outputs a default DMA channel value upon power-up; an interrupt level register, coupled to said computer system data bus, for storing an interrupt level value for the device, wherein said interrupt level register outputs a default interrupt level value upon power-up; and control logic, coupled to said first storage means, said computer system address bus and said computer system data bus, wherein said control logic: upon detecting activity on said computer system data bus characteristic of a computer system attempting to assign I/O addresses to a device, disables said device and allowes a computer system to write to said first storage means an I/O address; upon detecting activity on said computer system data bus characteristic of a computer system attempting to assign DMA channel value to a device, allows a computer system to write to said DMA channel register a DMA channel value; and upon detecting activity on said computer system data bus characteristic of a computer system attempting to assign interrupt level value to a device, allows a computer system to write to said interrupt level register an interrupt level value.
Claim 2
Dependent Claim
280 words
A backward compatible plug and play device for adaptive use with a computer of either a PNP or a legacy non-PNP type having system data and address busses, said device being coupled to said computer system data and address busses, said device comprising: first storage means, coupled to said computer system data bus, for storing an I/O address for the device, wherein said first storage means outputs a default I/O address upon power-up; a DMA channel register, coupled to said computer system data bus, for storing a DMA channel value for the device, wherein said DMA channel register outputs a default DMA channel value upon power-up; an interrupt level register, coupled to said computer system data bus, for storing an interrupt level value for the device, wherein said interrupt level register outputs a default interrupt level value upon power-up; and control logic, coupled to said first storage means, said computer system address bus and said computer system data bus, wherein said control logic: upon detecting activity on said computer system data bus characteristic of a computer system attempting to assign I/O addresses to a device, disables said device and allowes a computer system to write to said first storage means an I/O address; upon detecting activity on said computer system data bus characteristic of a computer system attempting to assign DMA channel value to a device, allows a computer system to write to said DMA channel register a DMA channel value; and upon detecting activity on said computer system data bus characteristic of a computer system attempting to assign interrupt level value to a device, allows a computer system to write to said interrupt level register an interrupt level value.
Claim 3
Dependent Claim
105 words
The device according to claim 1, wherein said control logic comprises: a linear feedback shift register, coupled to said address bus and a write signal from said computer system, for receiving an initiation key comprising a predetermined data sequence; and a comparator, coupled to said linear feedback shift register, for comparing a received data sequence from said linear feedback shift register with the predetermined data sequence, said comparator outputting a comparison signal when a received data sequence is comparable to the predetermined data sequence, wherein said comparison signal indicates an attempt by the computer system to initiate a routine to assign I/O addresses to devices.
Claim 4
Dependent Claim
80 words
The device according to claim 2, wherein said control logic further comprises: a multiplexer, coupled to a high level logic signal, for generating a high level logic signal as a device enable signal upon reset and power-up, said multiplexer having another input coupled to said system data bus for receiving a signal characteristic of a computer system attempting to enable a device after assigning an I/O address, said multiplexer receiving as a switching signal said comparison signal from said comparator.
Claim 5
Dependent Claim
65 words
The device according to claim 3, wherein said control logic further comprises: an activation register, coupled to said computer system data bus and said multiplexer, for detecting a signal from said computer system indicating an attempt by said computer system to activate a device after assigning an I/O address, said activation register outputting a signal to said device and said multiplexer indicative of such detection.
Claim 6
Dependent Claim
43 words
The device according to claim 4, wherein said control logic further comprises: a decoder, coupled to said computer system address bus, for detecting a computer system address corresponding to a command for activating a device and outputting a signal indicative of such detection.
Claim 7
Independent Claim
147 words
A method for adaptively operating a backward compatible plug and play device with a computer of either a PNP or a legacy non-pNP type having system data and address busses, said device being coupled to said computer system data and address busses, said method comprising the steps of: storing, in a first storage means coupled to said computer system data bus, a default I/O address upon power-up; storing, in a DMA channel register coupled to said computer system data bus, a default DMA channel value upon power-up; storing, in an interrupt level register coupled to said computer system data bus, a default interrupt level value upon power-up; detecting activity on said computer system data bus characteristic of a computer system attempting to assign I/O addresses to devices; and allowing a computer system to write to said first storage means an I/O address upon detection of said activity.
Claim 8
Independent Claim
147 words
A method for adaptively operating a backward compatible plug and play device with a computer of either a PNP or a legacy non-pNP type having system data and address busses, said device being coupled to said computer system data and address busses, said method comprising the steps of: storing, in a first storage means coupled to said computer system data bus, a default I/O address upon power-up; storing, in a DMA channel register coupled to said computer system data bus, a default DMA channel value upon power-up; storing, in an interrupt level register coupled to said computer system data bus, a default interrupt level value upon power-up; detecting activity on said computer system data bus characteristic of a computer system attempting to assign I/O addresses to devices; and allowing a computer system to write to said first storage means an I/O address upon detection of said activity.
Claim 9
Dependent Claim
17 words
The method of claim 6, further comprising the step of: disabling said device upon detection said activity.
Claim 10
Dependent Claim
79 words
The method of claim 6, further comprising the step of: receiving in a linear feedback shift register, an initiation key comprising a predetermined data sequence, comparing a received data sequence from said linear feedback shift register with the predetermined data sequence, and outputting a comparison signal when a received data sequence is comparable to the predetermined data sequence, wherein said comparison signal indicates an attempt by the computer system to initiate a routine to assign I/O addresses to devices.
Claim 11
Dependent Claim
49 words
The method of claim 8, further comprising the steps of: generating a device enable signal upon reset and powerup, receiving a characteristic signal of a computer system attempting to enable a device after assigning an I/O address, and terminating the device enable signal upon reception of the characteristic signal.
Claim 12
Dependent Claim
47 words
The method of claim 9 further comprising the steps of: detecting a signal from said computer system indicating an attempt by said computer system to activate a device after assigning an I/O address, and outputting a signal to said device and said multiplexer indicative of such detection.
Claim 13
Dependent Claim
38 words
The method of claim 10, further comprising the step of: detecting on the computer system address bus, a computer system address corresponding to a command signal for activating a device, and outputting a signal indicative of such detection.
Claim 14
Dependent Claim
47 words
The method of claim 7, further comprising the steps of: detecting activity on said computer system data bus characteristic of a computer system attempting to assign DMA channel values to devices and allowing a computer system to write to said DMA channel register a DMA channel value.
Claim 15
Dependent Claim
47 words
The method of claim 7, further comprising the steps of: detecting activity on said computer system data bus characteristic of a computer system attempting to assign interrupt level values to devices and allowing a computer system to write to said interrupt level register an interrupt level value.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-26 | 2000-11-25 | 2001-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-26 | 2004-11-25 | 2005-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-26 | 2008-11-25 | 2009-05-27 | $7700.00 | Window Closed / Lapsed |