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US4755934A Expired / Lapsed US ⏱️ 0.0 years remaining

System for selecting an address in an input/output board

Assignee: Fanuc Corp
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Filing: 1985-03-15
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Granted: 1988-07-05
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Expires: 2005-03-15
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Abstract

Abstract An input/output board (10 to 12) address selection system selects a desired address in the pluralities of input and output boards (10 to 12) connected to a common bus (6) of an input/output interface unit (1) connected via a serial data transmission system to a main control unit (60). A programmable address translation circuit (5) is provided for deriving a slot select signal (s1 to s16) and an in-board address (BA) from an address for an input/output board accessing address which is provided from a control circuit (2) of the input/output interface unit (1). One of the input and output boards (10 to 12) is selected by the slot select signal (s1 to s16), and one of the addresses in the selected input or output board is selected by the in-board address (BA).

Inventors

  • 👤 Michiya Inoue

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 22:23
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0653

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 253 words
An input/output board address selection system for selecting a desired address in pluralities of input and output boards connected to a common bus of an input/output interface unit which is connected via a serial data transmission system with a main control unit including a microcomputer and a RAM, comprising: a control circuit in the input/output interface unit, said control circuit providing an access address for accessing the input and output boards; and a programmable address translation circuit, coupled to the common bus and said control circuit, for creating a slot select signal and an in-board address from the access address which is provided from said control circuit of the input/output interface unit, one of the pluralities of input and output boards being selected by the slot select signal from said programmable address translation circuit, and one of the addresses in the selected input or output board being selected by the in-board address which is provided on the common bus from said programmable address translation circuit, said programmable address translation circuit including: a memory coupled to said control circuit, said memory including memory areas respectively corresponding to the input and output boards, each of the memory areas including slot select information and an in-board address, said memory for reading out selected slot select information and a corresponding in-board address based on the access address provided by said control circuit; a decoder, coupled to said memory, for receiving the selected slot select information read out from said memory and for generating the slot select signal.
Claim 2
Dependent Claim 253 words
An input/output board address selection system for selecting a desired address in pluralities of input and output boards connected to a common bus of an input/output interface unit which is connected via a serial data transmission system with a main control unit including a microcomputer and a RAM, comprising: a control circuit in the input/output interface unit, said control circuit providing an access address for accessing the input and output boards; and a programmable address translation circuit, coupled to the common bus and said control circuit, for creating a slot select signal and an in-board address from the access address which is provided from said control circuit of the input/output interface unit, one of the pluralities of input and output boards being selected by the slot select signal from said programmable address translation circuit, and one of the addresses in the selected input or output board being selected by the in-board address which is provided on the common bus from said programmable address translation circuit, said programmable address translation circuit including: a memory coupled to said control circuit, said memory including memory areas respectively corresponding to the input and output boards, each of the memory areas including slot select information and an in-board address, said memory for reading out selected slot select information and a corresponding in-board address based on the access address provided by said control circuit; a decoder, coupled to said memory, for receiving the selected slot select information read out from said memory and for generating the slot select signal.
Claim 3
Dependent Claim 263 words
An address selection system for selecting a desired address from among input boards and output boards coupled to a serial data transmission system, comprising: a common bus coupled to the input and output boards; a control circuit for generating an access address for accessing one of the input and output boards; an address translation circuit, coupled to said control circuit and said common bus, for generating a slot select signal and an in-board address based on the access address generated by said control circuit; and transmission lines connected to said address translation circuit and respectively connected to the input and output boards, one of the input and output boards being selected by the slot select signal generated by said address translation circuit, the slot select signal being carried on the one of said transmission lines corresponding to the selected one of the input and output boards, and one of the addresses in the selected input or putput board being selected by the in-board address which is provided on said common bus by said address translation circuit, said address translation circuit including: a memory coupled to said control circuit, said memory including memory areas respectively corresponding to the input and output boards, each of the memory areas including slot select information and an in-board address, said memory for reading out selected slot select information and a corresponding in-board address based on the access address provided by said control circuit;and a decoder, coupled to said memory, for receiving the selected slot select information read out from said memory and for generating the slot selects signal.
Claim 4
Dependent Claim 263 words
An address selection system for selecting a desired address from among input boards and output boards coupled to a serial data transmission system, comprising: a common bus coupled to the input and output boards; a control circuit for generating an access address for accessing one of the input and output boards; an address translation circuit, coupled to said control circuit and said common bus, for generating a slot select signal and an in-board address based on the access address generated by said control circuit; and transmission lines connected to said address translation circuit and respectively connected to the input and output boards, one of the input and output boards being selected by the slot select signal generated by said address translation circuit, the slot select signal being carried on the one of said transmission lines corresponding to the selected one of the input and output boards, and one of the addresses in the selected input or putput board being selected by the in-board address which is provided on said common bus by said address translation circuit, said address translation circuit including: a memory coupled to said control circuit, said memory including memory areas respectively corresponding to the input and output boards, each of the memory areas including slot select information and an in-board address, said memory for reading out selected slot select information and a corresponding in-board address based on the access address provided by said control circuit;and a decoder, coupled to said memory, for receiving the selected slot select information read out from said memory and for generating the slot selects signal.
Claim 5
Dependent Claim 77 words
An address selection system according to claim 2, further comprising an input and output board mounting structure having slots formed therein for receiving the input and output boards, said input and output board mounting structure having connectors formed thereon corresponding to said slots, said connectors being connected to said common bus and being respectively connected to said transmission lines, so that each of said connectors is connected to receive a corresponding one of the slot select signals.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-07-05 1992-01-04 1992-07-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-07-05 1996-01-04 1996-07-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-07-05 2000-01-04 2000-07-05 $7700.00 Window Closed / Lapsed

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