Dynamic device address assignment mechanism for a data processing system

Claim 2

In a peripheral control unit for coupling a peripheral device to a processor by means of a processor I/O bus having data, address and control lines, wherein the peripheral device is identified by means of a device address assigned thereto, a dynamic device address assignment mechanism comprising: a device address register for holding the device address assigned to the peripheral device; and circuitry responsive to the appearance of a unique I/O command on the I/O bus and to the activation of a unique set of the I/O bus data lines by the processor for loading into the device address register an address supplied to the I/O bus address lines by the processor for enabling such address to become the assigned device address.

Claim 3

In a peripheral control unit for coupling a peripheral device to a processor by means of a processor I/O bus having data, address and control lines, wherein the peripheral device is identified by means of a device address assigned thereto, a dynamic device address assignment mechanism comprising: a device address register for holding the device address assigned to the peripheral device; address comparison circuitry for comparing the address on the I/O bus address lines with the assigned device address stored in the device address register for enabling the control unit to receive signals from the processor when the address on the I/O bus address lines is the same as such assigned address; and signal-responsive circuitry responsive to the appearance of a unique I/O command on the I/O bus and to the activation of a unique set of the I/O bus data lines by the processor for loading into the device address register an address supplied to the I/O bus address lines by the processor for enabling such address to become the assigned device address.

Claim 4

In a peripheral control unit for coupling a peripheral device to a processor by means of a processor I/O bus having data, address and control lines, wherein the peripheral device is identified by means of a device address assigned thereto, a dynamic device address assignment mechanism comprising: a device address register for holding the device address assigned to the peripheral device; address comparison circuitry for comparing the address on the I/O bus address lines with the assigned device address stored in the device address register for enabling the control unit to receive signals from the processor when the address on the I/O bus address lines is the same as such assigned address; and signal-responsive circuitry responsive to the appearance of a unique I/O command on the I/O bus and to the activation of a unique set of the I/O bus data lines by the processor for loading into the device address register an address supplied to the I/O bus address lines by the processor for enabling such address to become the assigned device address.

Claim 5

In a peripheral control unit for coupling a peripheral device to a processor by means of a processor I/O bus having data, address and control lines, wherein the peripheral device is identified by means of a device address assigned thereto, a dynamic device address assignment mechanism comprising: a device address register for holding the device address assigned to the peripheral device; address comparison circuitry for comparing the address on the I/O bus address lines with the assigned device address stored in the device address register for enabling the control unit to receive signals from the processor when the address on the I/O bus address lines is the same as such assigned address; and signal-responsive circuitry responsive to the appearance of a unique I/O command on the I/O bus and to the activation of a particular one of the I/O bus data lines by the processor for loading into the device address register the address then appearing on the I/O bus address lines for enabling such address to become the assigned device address.

Claim 6

In a peripheral control unit for coupling a peripheral device to a processor by means of a processor I/O bus having data, address and control lines, wherein the peripheral device is identified by means of a device address assigned thereto, a dynamic device address assignment mechanism comprising: a device address register for holding the device address assigned to the peripheral device; address comparison circuitry for comparing the address on the I/O bus address lines with the assigned device address stored in the device address register for enabling the control unit to receive signals from the processor when the address on the I/O bus address lines is the same as such assigned address; and signal-responsive circuitry responsive to the appearance of a unique I/O command on the I/O bus and to the activation of a particular one of the I/O bus data lines by the processor for loading into the device address register the address then appearing on the I/O bus address lines for enabling such address to become the assigned device address.

Claim 7

A dynamic device address assignment mechanism in accordance with claim 2 wherein the signal-responsive circuitry includes decoder circuitry coupled to the I/O bus for producing a decoder output signal when the unique I/O command appears on the I/O bus.

Claim 8

A dynamic device address assignment mechanism in accordance with claim 4 wherein: the signal-responsive circuitry further includes a logic circuit having a first input coupled to the output of the decoder circuitry, a second input coupled to said particular one of the I/O bus data lines and an output coupled to the device address register for supplying a load signal to the device address register when both the decoder output signal is present and the particular data line to which the first input of the logic circuit is coupled is activated by the processor.

Claim 9

In a data processing system having a processor, a processor I/O bus, a plurality of peripheral devices and a plurality of control units for coupling the peripheral devices to the processor I/O bus, wherein each peripheral device is identified by means of a different device address assigned thereto, a dynamic device address assignment apparatus comprising: a first device address register located in a first control unit for holding the device address assigned to its peripheral device; a second device address register located in a second control unit for holding the device address assigned to its peripheral device; circuitry responsive to the appearance of a unique I/O command on the I/O bus and to the activation of a first unique set of the data lines of the I/O bus by the processor for loading into the first device address register a first address supplied to the I/O bus by the processor for enabling such address to become the assigned device address; and circuitry responsive to the appearance of the unique I/O command on the I/O bus and to the activation of a second and different unique set of the data lines of the I/O bus by the processor for loading into the second device address register a second address supplied to the I/O bus by the processor for enabling such address to become the assigned device address.

Claim 10

In a data processing system having a processor, a processor I/O bus, a plurality of peripheral devices and a plurality of control units for coupling the peripheral devices to the processor I/O bus, wherein each peripheral device is identified by means of a different device address assigned thereto, a dynamic device address assignment apparatus comprising: a first device address register located in a first control unit for holding the device address assigned to its peripheral device; a second device address register located in a second control unit for holding the device address assigned to its peripheral device; circuitry responsive to the appearance of a unique I/O command on the I/O bus and to the activation of a first unique set of the data lines of the I/O bus by the processor for loading into the first device address register a first address supplied to the I/O bus by the processor for enabling such address to become the assigned device address; and circuitry responsive to the appearance of the unique I/O command on the I/O bus and to the activation of a second and different unique set of the data lines of the I/O bus by the processor for loading into the second device address register a second address supplied to the I/O bus by the processor for enabling such address to become the assigned device address.