US4253087A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-assigning address system
Assignee: NESTAR SYSTEMS Inc
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Filing: 1979-03-08
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Granted: 1981-02-24
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Expires: 1999-03-08
Abstract
Abstract An address system for selectively addressing any one of a number of serially connected addressable units from one or more control units by means of an identical signaling device, such as an electronic circuit, positioned at each device location. The signaling device has an input connector and an output connector for connecting each signaling device to a parallel bus which connects each signaling device to the other signaling devices in series. The signaling device operates in the same manner at each addressable unit location by permuting signals appearing on the input connector, and connecting the permuted input connector signals to the corresponding output connector of the same signaling device. The output connector of the permuted signaling device is then connected via a parallel bus to the input connector of the next signaling device. The signaling device thus operates in the same manner at each addressable unit location.
Inventors
- 👤 Harry J. Saal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 23:31
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0669; G06F12/0676; H; H04; H04Q; H04Q9/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
335 words
A system for selectively addressing any one of a number of addressable units connected one to the other in series, comprising: a control unit, electrically connected to each of said addressable units by means of an electronic circuit, having N signal carrying conductors logically divided into at least two groups of conductors forming at least a group 1 and a group 2 of conductors, respectively with N being less than the number of addressable units; at least two address lines for each of said addressable units, the number of said address lines being equal to the number of logical groups of conductors, with each of said address lines being connected to the same one of said conductors in each of said logical groups of conductors of each one of said circuits; said circuits each having N input connections and N output connections, with said N input and said N output connections being each logically divided into at least two groups of connections, and with said N input connections of one circuit being connected to the N output connections of the same circuit by means of said N conductors, and with said output connections of said same circuit being operatively connected to the input connections of the next serially connected circuit by means of a parallel bus, and wherein said N conductors of each of said logical groups of conductors of said circuit connects said input connections to said output connections of the same circuit via a rotation within each of said logical groups, such that a signal appearing on an input connection within a group of input connections appears in a rotated position on an output connection within the corresponding group of output connections, such that when said control unit signals said circuit with at least two signals on at least two of said input connections connected to at least two of said conductors which are connected to at least two of said address lines, one of said serially connected addressable units will be addressed.
Claim 2
Independent Claim
335 words
A system for selectively addressing any one of a number of addressable units connected one to the other in series, comprising: a control unit, electrically connected to each of said addressable units by means of an electronic circuit, having N signal carrying conductors logically divided into at least two groups of conductors forming at least a group 1 and a group 2 of conductors, respectively with N being less than the number of addressable units; at least two address lines for each of said addressable units, the number of said address lines being equal to the number of logical groups of conductors, with each of said address lines being connected to the same one of said conductors in each of said logical groups of conductors of each one of said circuits; said circuits each having N input connections and N output connections, with said N input and said N output connections being each logically divided into at least two groups of connections, and with said N input connections of one circuit being connected to the N output connections of the same circuit by means of said N conductors, and with said output connections of said same circuit being operatively connected to the input connections of the next serially connected circuit by means of a parallel bus, and wherein said N conductors of each of said logical groups of conductors of said circuit connects said input connections to said output connections of the same circuit via a rotation within each of said logical groups, such that a signal appearing on an input connection within a group of input connections appears in a rotated position on an output connection within the corresponding group of output connections, such that when said control unit signals said circuit with at least two signals on at least two of said input connections connected to at least two of said conductors which are connected to at least two of said address lines, one of said serially connected addressable units will be addressed.
Claim 3
Dependent Claim
87 words
An address system as set forth in claim 1 wherein the logical division of signal carrying conductors is such that the number of conductors in each of the respective logical groups of conductors of said circuit is each relatively prime with respect to the number of conductors in each of the other logical groups of conductors and wherein the maximum number of selectively addressable units for said address system is equal to the product of the numbers of elements in each of said relatively prime logical groups.
Claim 4
Independent Claim
358 words
A system for selectively addressing any one of a number of addressable units connected one to the other in series, comprising: a control unit, operatively connected to each of said addressable units by means of a signaling device, having N signal carrying elements logically divided into at least two groups of elements forming at least a group 1 and a group 2 of signal carrying elements, respectively, with N being less than the number of addressable units; at least two address lines for each of said addressable units, the number of said address lines being equal to the number of logical groups of said signal carrying elements, with each one of said address lines being connected to the same one of said signal carrying elements in each of said groups of each one of said signaling devices; said signaling devices each having an input connector with N input connections and an output connector with N output connections, with said N input and said N output connections being each logically divided into at least two groups of connections, and with said input connections of one signaling device being connected to the output connections of the same signaling device by means of said N signal carrying elements, and with said output connections of said same signaling device being operatively connected to the input connections of the next serially connected signaling device by means of a parallel bus, and wherein said N signal carrying elements of each of said logical groups of elements of said signaling device connect said input connections to said output connections of the same signaling device via a rotation within each of said groups, such that a signal appearing on an input connection within a group of input connections appears in a rotated position on an output connection within the corresponding group of output connections, such that when said control unit signals said signaling device with at least two signals on at least two of said input connections connected to at least two signal carrying elements which are connected to at least two of said address lines, one of said serially connected addressable units will be addressed.
Claim 5
Independent Claim
358 words
A system for selectively addressing any one of a number of addressable units connected one to the other in series, comprising: a control unit, operatively connected to each of said addressable units by means of a signaling device, having N signal carrying elements logically divided into at least two groups of elements forming at least a group 1 and a group 2 of signal carrying elements, respectively, with N being less than the number of addressable units; at least two address lines for each of said addressable units, the number of said address lines being equal to the number of logical groups of said signal carrying elements, with each one of said address lines being connected to the same one of said signal carrying elements in each of said groups of each one of said signaling devices; said signaling devices each having an input connector with N input connections and an output connector with N output connections, with said N input and said N output connections being each logically divided into at least two groups of connections, and with said input connections of one signaling device being connected to the output connections of the same signaling device by means of said N signal carrying elements, and with said output connections of said same signaling device being operatively connected to the input connections of the next serially connected signaling device by means of a parallel bus, and wherein said N signal carrying elements of each of said logical groups of elements of said signaling device connect said input connections to said output connections of the same signaling device via a rotation within each of said groups, such that a signal appearing on an input connection within a group of input connections appears in a rotated position on an output connection within the corresponding group of output connections, such that when said control unit signals said signaling device with at least two signals on at least two of said input connections connected to at least two signal carrying elements which are connected to at least two of said address lines, one of said serially connected addressable units will be addressed.
Claim 6
Dependent Claim
88 words
An address system as set forth in claim 3 wherein the logical division of signal carrying elements is such that the number of elements in the respective logical groups of elements of said signal carrying elements are each relatively prime with respect to the number of elements in each of the other logical groups of signal carrying elements wherein the maximum number of selectively addressable units for said address system is equal to the product of the number of elements in each of said relatively prime logical groups.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-02-24 | 1984-08-25 | 1985-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-02-24 | 1988-08-25 | 1989-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-02-24 | 1992-08-25 | 1993-02-24 | $7700.00 | Window Closed / Lapsed |