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US5629901A
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Multi write port register
Assignee: International Business Machines Corp
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Filing: 1995-12-05
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Granted: 1997-05-13
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Expires: 2015-12-05
Abstract
Abstract A multi-write port register is provided with a local clock buffer (LCB) to control a gate on the input port to reduce potential timing hazards. The LCB provides flexible logic function and is controlled by a clock and word-line inputs. In addition, the LCB may also have bit-line and/or field mask inputs. The LCB handles all the timing critical functions that all the Word Lines (WLs) previously performed in conventional multi-write port registers, thus providing a substantial performance increase.
Inventors
- 👤 Stanley T. Ho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 03:10
CPC Classifications
G; G06; G06F; G06F9/00; G11; G11C; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
125 words
A multi-write port register file comprising: a plurality of gates connected between multiple write ports and a corresponding plurality of cells of the multi-write port register file; and a plurality of local clock buffers connected to control selected ones of said gates, the number of said local clock buffers corresponding to a number of write fields for the multi-write port register, each local clock buffer generating a write-enable signal to corresponding selected ones of said gates which write-enable signal is common among all cells contained in the same write field, said local clock buffer incorporating a fixed time delay between a system clock and an output of the local clock buffer to reduce timing hazards in writing data to the register in succeeding data cycles.
Claim 2
Dependent Claim
125 words
A multi-write port register file comprising: a plurality of gates connected between multiple write ports and a corresponding plurality of cells of the multi-write port register file; and a plurality of local clock buffers connected to control selected ones of said gates, the number of said local clock buffers corresponding to a number of write fields for the multi-write port register, each local clock buffer generating a write-enable signal to corresponding selected ones of said gates which write-enable signal is common among all cells contained in the same write field, said local clock buffer incorporating a fixed time delay between a system clock and an output of the local clock buffer to reduce timing hazards in writing data to the register in succeeding data cycles.
Claim 3
Dependent Claim
85 words
The multi-write port register file recited in claim 1 wherein write ports for a cell of the register comprise a plurality of write-port bit lines and a plurality of write-port word lines, each of said write-port bit lines being connected to a source of a corresponding field effect transistor and each of said write-port word lines being connected to a gate of a corresponding field effect transistor, drains of said field effect transistors being connected in common to one of said gates for that cell.
Claim 4
Dependent Claim
72 words
The multi-write port register file recited in claim 2 wherein the local clock buffer comprises: combinatorial logic for generating a write select signal; a tri-state buffer controlled by said write select signal to pass one phase of a system clock; and delay means connected to the output of said tri-state buffer for delaying the system clock passed by the tri-state buffer, the output of the delay means being connected to said gate.
Claim 5
Dependent Claim
39 words
The multi-write port register file recited in claim 3 wherein the combinatorial logic receives a plurality of write-port write lines as inputs and generates said write select signal as a logical sum of signals on the write-port write lines.
Claim 6
Dependent Claim
33 words
The multi-write port register file recited in claim 3 wherein the local clock buffer is connected to a plurality of normal write-ports, a plurality of reset write-ports and at least one set write-port.
Claim 7
Dependent Claim
41 words
The multi-write port register file recited in claim 5 wherein said combinatorial logic receives as inputs signals from said normal write-ports, said reset write-ports and said set write-port and generates said write select signal as a logical sum of said signals.
Claim 8
Dependent Claim
43 words
The multi-write port register file recited in claim 3 wherein said local clock buffer is connected to a multi-writeported register file consisting of multiple disjoint segment fields, there being multiple stacks of local clock buffers each associated with one of the segment fields.
Claim 9
Dependent Claim
23 words
The multi-write port register file recited in claim 7 further comprising a segment mask signal associated with each of the multiple write ports.
Claim 10
Dependent Claim
83 words
The multi-write port register file recited in claim 3 wherein said local clock buffer is connected to a register file with a plurality of sticky-1 write-ports, each sticky-1 write-port having a write-wordline and a bitline associated with it, wherein for a sticky-1 operation, a "1" will be written into a cell of the register file if data on the bitline is "1", but if the bitline is a "0", the write operation is suppressed and the cell will retain its previous data state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-12 | 2000-11-11 | 2001-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-12 | 2004-11-11 | 2005-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-12 | 2008-11-11 | 2009-05-13 | $7700.00 | Window Closed / Lapsed |