US5481495A
Expired / Lapsed
US
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Cells and read-circuits for high-performance register files
Assignee: International Business Machines Corp
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Filing: 1994-04-11
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Granted: 1996-01-02
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Expires: 2014-04-11
Abstract
Abstract A high-performance register file is implemented in a multi-block structure consisting of sub-arrays and associated multiplexing circuits. For a given port, the outputs of all multiplexer circuits are dotted together to form a single global output. The multiplexer circuits may be completely external to the cells ("standard" approach), or distributed and integrated into the cells ("alternate" approach). The register cells arranged as such, may or may not contain extra latches, pass gates, and controls arranged so that the file may be fully tested via LSSD.
Inventors
- 👤 Walter H. Henkels
- 👤 Wei Hwang
- 👤 Terry I. Chappell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 03:02
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
86 words
A multi-port register file employing single-ended reading and writing, comprising: a plurality of read-ports and a plurality of write-ports; an assembly of blocks, each block consisting of a sub-array of multi-port register file cells and associated multiplexing circuits; write bit lines extending a full height of the register file with no partitioning along the write bit lines; and for a given read-port, outputs of all multiplexing circuits from all the blocks being dot-ORed together onto a single global output line for an entire, full register file.
Claim 2
Dependent Claim
86 words
A multi-port register file employing single-ended reading and writing, comprising: a plurality of read-ports and a plurality of write-ports; an assembly of blocks, each block consisting of a sub-array of multi-port register file cells and associated multiplexing circuits; write bit lines extending a full height of the register file with no partitioning along the write bit lines; and for a given read-port, outputs of all multiplexing circuits from all the blocks being dot-ORed together onto a single global output line for an entire, full register file.
Claim 3
Dependent Claim
27 words
The register file recited in claim 1 wherein the multiplexing circuits in each block are completely external to the sub-array of register file cells of each block.
Claim 4
Dependent Claim
28 words
The register file recited in claim 1 wherein the multiplexing circuits in each block are distributed and integrated into the sub-array of register file cells of each block.
Claim 5
Dependent Claim
36 words
The register file recited in claim 1 further comprising extra latches, pass gates, and controls included within every register file cell, for the purpose of enabling full LSSD testing of all registers of the register file.
Claim 6
Dependent Claim
97 words
A multi-port register file employing single-ended reading and writing, comprising: a plurality of read-ports and a plurality of write-ports; an assembly of blocks, each block consisting of a sub-array of multi-port register file cells and associated dynamic multiplexing circuits compatible with self-resetting CMOS circuits; write bit lines extending a full height of the register file with no partitioning along the write bit lines; and for a given read-port, outputs of the multiplexing circuits from all the blocks are dot-ORed together onto a single global output line with a single read decoder for an entire, full register file.
Claim 7
Dependent Claim
97 words
A multi-port register file employing single-ended reading and writing, comprising: a plurality of read-ports and a plurality of write-ports; an assembly of blocks, each block consisting of a sub-array of multi-port register file cells and associated dynamic multiplexing circuits compatible with self-resetting CMOS circuits; write bit lines extending a full height of the register file with no partitioning along the write bit lines; and for a given read-port, outputs of the multiplexing circuits from all the blocks are dot-ORed together onto a single global output line with a single read decoder for an entire, full register file.
Claim 8
Dependent Claim
36 words
The register file recited in claim 5 further comprising within every register file cell, extra latches, pass gates, and controls included for the purpose of enabling full LSSD testing of all registers of the register file.
Claim 9
Dependent Claim
119 words
A multi-port register file employing single-ended reading and writing, comprising: a plurality of read-ports and a plurality of write-ports; an assembly of blocks, each block consisting of a sub-array of multi-port register file cells and associated dynamic multiplexing circuits compatible with self-resetting CMOS circuits, said multiplexing circuits being completely external to the cells of the sub-array; write bit lines extending a full height of the register file and connected to each cell of each sub-array of cells with no partitioning along the write bit lines; and for a given read-port, outputs of the multiplexing circuits from all the blocks are dot-ORed together onto a single global output line with a single read decoder for an entire, full register file.
Claim 10
Dependent Claim
119 words
A multi-port register file employing single-ended reading and writing, comprising: a plurality of read-ports and a plurality of write-ports; an assembly of blocks, each block consisting of a sub-array of multi-port register file cells and associated dynamic multiplexing circuits compatible with self-resetting CMOS circuits, said multiplexing circuits being completely external to the cells of the sub-array; write bit lines extending a full height of the register file and connected to each cell of each sub-array of cells with no partitioning along the write bit lines; and for a given read-port, outputs of the multiplexing circuits from all the blocks are dot-ORed together onto a single global output line with a single read decoder for an entire, full register file.
Claim 11
Dependent Claim
120 words
A multi-port register file employing single-ended reading and writing, comprising: a plurality of read-ports and a plurality of write-ports; an assembly of blocks, each block consisting of a sub-array of multi-port register file cells and associated dynamic multiplexing circuits compatible with self-resetting CMOS circuits, said multiplexing circuits being distributed and integrated into the cells of the sub-array; write bit lines extending a full height of the register file and connected to each cell of each sub-array of cells with no partitioning along the write bit lines; and for a given read-port, outputs of the multiplexing circuits from all the blocks are dot-ORed together onto a single global output line with a single read decoder for an entire, full register file.
Claim 12
Dependent Claim
120 words
A multi-port register file employing single-ended reading and writing, comprising: a plurality of read-ports and a plurality of write-ports; an assembly of blocks, each block consisting of a sub-array of multi-port register file cells and associated dynamic multiplexing circuits compatible with self-resetting CMOS circuits, said multiplexing circuits being distributed and integrated into the cells of the sub-array; write bit lines extending a full height of the register file and connected to each cell of each sub-array of cells with no partitioning along the write bit lines; and for a given read-port, outputs of the multiplexing circuits from all the blocks are dot-ORed together onto a single global output line with a single read decoder for an entire, full register file.
References Cited (Backward Citations)
US5315178A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-01 | 1999-07-03 | 2000-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-01 | 2003-07-03 | 2004-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-01 | 2007-07-03 | 2008-01-02 | $7700.00 | Window Closed / Lapsed |