Multiport DRAM

Claim 2

A multiport DRAM comprising: a RAM section having a plurality of alternately arranged RAM blocks for constructing a first RAM section and a second RAM section, respectively; a SAM section having a plurality of SAM blocks for constructing a first SAM section and a second SAM section, respectively, so as to correspond to the respective RAM blocks; and a data transfer control section disposed between said RAM section and said SAM section, for controlling data transfer between said RAM section and said SAM section, an inversion side and a non-inversion side of mutually complementary bit lines of said plural RAM block being reversed for each block; adjacent bit lines of the RAM blocks belonging to the first RAM section and the RAM block belonging to the adjacent second RAM section being connected in common to any one of a data line of the SAM block corresponding to the RAM block belonging to the first RAM section and a data line of the SAM block corresponding to the RAM block belonging to the adjacent second RAM section; and said data transfer control section including four switches for enabling data transfer from either of the first RAM section and the second RAM section to either of the first SAM section and the second SAM section by controlling conduction of the respective bit lines of the RAM block belonging to the first RAM section and the RAM block of the adjacent second RAM section, respectively and independently.

Claim 3

The multiport DRAM of claim 1, wherein the adjacent bit lines of the adjacent RAM blocks are connected to logically same input/output lines through sense amplifiers and input/output gates of the blocks, respectively.

Claim 4

The multiport DRAM of claim 1, wherein mutually complementary data lines of said SAM section include a first line connected to the common junction point and a second line inverted relative to the first line via an inverter.

Claim 5

The multiport DRAM of claim 1, wherein the number of the SAM blocks is larger by one than that of the RAM blocks.

Claim 6

A multiport DRAM comprising: a RAM section composed of n-piece RAM blocks (a i ) (i=1, 2, . . . n) including a plurality of memory cells having a "0" most significant bit in column address and connected to a pair of bit lines (BL 0i ) and bar (BL 0i ), respectively, and n-piece RAM blocks (b i )(i=1, 2, . . . n) including a plurality of memory cells having a "1" most significant bit in column address and connected to a pair of bit lines (BL 1i ) and bar (BL 1i ), respectively; a SAM section composed of a first data register including first and second terminals and (n+1)-piece SAM blocks (c i )(i=1, . . . n+1) for inverting data inputted through the first terminal, storing the inverted data, and storing data inputted through the second terminal, and a second data register including third and fourth terminals and n-piece SAM blocks (d i )(i=1, . . . n) for inverting data inputted through the third terminal, storing the inverted data, and storing data inputted through the fourth terminal; a data transfer gate section including 4n-piece gate transistors (T ji )(j=1, . . . 4, i=1, . . . n) and first, second, third, and fourth control lines; the n-piece RAM blocks a i (i=1, . . . n) and the n-piece RAM blocks (b i )(i=1, . . . n) being juxtaposed alternately, and two adjacent bit lines of two pairs of bit lines of the two adjacent RAM blocks being arranged so that the data direction matches each other; the (n+1)-piece SAM blocks (c i )(i=1, . . . n+1) of the first data register and n-piece SAM blocks (d i )(i=1, . . . n) of the second data register being disposed alternately; gates of the gate transistors (T 1i )(i=1, . . . n) being connected to the first control line, either of sources and drains thereof being connected to either of the bit lines (BL 0i ) of the RAM blocks a i and the first terminals of the SAM blocks (c i ), respectively; gates of the gate transistors (T 2i ) (i=1, . . . n) being connected to the second control line, either of sources and drains thereof being connected to either of the bit lines bar (BL 0i ) and the third terminals of the SAM blocks (d i ), respectively; gates of the gate transistors (T 3i )(i=1, . . . n) being connected to the third control line, either of sources and drains thereof being connected to either of the bit lines bar (BL 1i ) of the RAM blocks (b i ) and the third terminals of the SAM blocks (d i ) respectively; and gates of the gate transistors (T 4i )(i=1, . . . n) being connected to the fourth control line, either of sources and drain thereof being connected to either of the bit lines (BL 1i ) of the RAM blocks (b i ) and the first terminals of the SAM blocks (c i+1 ), respectively.

Claim 7

A multiport DRAM comprising: a RAM section composed of n-piece RAM blocks (a i ) (i=1, 2, . . . n) including a plurality of memory cells having a "0" most significant bit in column address and connected to a pair of bit lines (BL 0i ) and bar (BL 0i ), respectively, and n-piece RAM blocks (b i )(i=1, 2, . . . n) including a plurality of memory cells having a "1" most significant bit in column address and connected to a pair of bit lines (BL 1i ) and bar (BL 1i ), respectively; a SAM section composed of a first data register including first and second terminals and (n+1)-piece SAM blocks (c i )(i=1, . . . n+1) for inverting data inputted through the first terminal, storing the inverted data, and storing data inputted through the second terminal, and a second data register including third and fourth terminals and n-piece SAM blocks (d i )(i=1, . . . n) for inverting data inputted through the third terminal, storing the inverted data, and storing data inputted through the fourth terminal; a data transfer gate section including 4n-piece gate transistors (T ji )(j=1, . . . 4, i=1, . . . n) and first, second, third, and fourth control lines; the n-piece RAM blocks a i (i=1, . . . n) and the n-piece RAM blocks (b i )(i=1, . . . n) being juxtaposed alternately, and two adjacent bit lines of two pairs of bit lines of the two adjacent RAM blocks being arranged so that the data direction matches each other; the (n+1)-piece SAM blocks (c i )(i=1, . . . n+1) of the first data register and n-piece SAM blocks (d i )(i=1, . . . n) of the second data register being disposed alternately; gates of the gate transistors (T 1i )(i=1, . . . n) being connected to the first control line, either of sources and drains thereof being connected to either of the bit lines (BL 0i ) of the RAM blocks a i and the first terminals of the SAM blocks (c i ), respectively; gates of the gate transistors (T 2i ) (i=1, . . . n) being connected to the second control line, either of sources and drains thereof being connected to either of the bit lines bar (BL 0i ) and the third terminals of the SAM blocks (d i ), respectively; gates of the gate transistors (T 3i )(i=1, . . . n) being connected to the third control line, either of sources and drains thereof being connected to either of the bit lines bar (BL 1i ) of the RAM blocks (b i ) and the third terminals of the SAM blocks (d i ) respectively; and gates of the gate transistors (T 4i )(i=1, . . . n) being connected to the fourth control line, either of sources and drain thereof being connected to either of the bit lines (BL 1i ) of the RAM blocks (b i ) and the first terminals of the SAM blocks (c i+1 ), respectively.