Video memory device

Claim 2

A video memory device comprising a RAM and a plurality of SAMs, wherein said RAM is constructed of a plurality of memory cells disposed in a matrix having a plurality of rows and columns, one of said memory cells being selected through designation by row and column addresses, and one bit data being transmitted between said selected memory cell and a RAM port, said one bit data being input/output to/from the RAM port; and wherein each of said SAMs is constructed as a multi-word length type and connected to a plurality of columns of said RAM, and each of said SAMs transmits/receives data to/from said memory cells belonging to said columns connected to said each of said SAMs, and each of said SAMs has one SAM port for inputting/outputting data and each of said SAMs inputs/outputs data from/to the SAM port, and said plurality of SAMs is adapted to output data at the same time, whereby the data in said RAM are input/output as multi-bit data via said plurality of SAM ports of said plurality of SAMs.

Claim 3

A video memory device according to claim 1, wherein each of said plurality of columns is connected to one of said SAMs.

Claim 4

A video memory device according to claim 1, wherein each of said plurality of columns is multiple-connected to a plurality of said SAMs.

Claim 5

A video memory device according to claim 1, wherein each of said SAMs is divided into first and second groups, the first group being accessed during the first half of a serial access time of said SAMs and the second group being accessed during the second half of said serial access time, and while one of said first and second groups serially outputs/inputs data, the other of said first and second groups transmits/receives data to/from said RAM.

Claim 6

A video memory device according to claim 4, wherein each of said plurality of SAMs is made capable of being set at one of serial input and output modes, independently of each other.

Claim 7

A video memory device according to claim 5, wherein said first and second groups are alternately connected to said SAM ports by split selectors for the serial data input/output.

Claim 8

A video memory device according to claim 4, wherein said first and second groups are alternately connected via split selectors to said SAM ports for the serial data input/output.

Claim 9

A video memory device according to claim 1, wherein each of said plurality of SAMs is made capable of being set at one of serial input and output modes, independently of each other.

Claim 10

A video memory device according to claim 1, wherein each of said plurality of SAMs is made capable of being set with a serial cycle time independently of each other, and each of said SAMs is made capable of being set with a serial cycle time asynchronously.

Claim 11

A video memory device comprising a RAM and a plurality of SAMs, wherein said RAM is constructed of a plurality of memory cells disposed in a matrix having a plurality of rows and columns, one of said memory cells being selected through designation by row and column addresses, and one bit data being transmitted between said selected memory cell and a RAM port, said one bit data being input/output to/from the RAM port; and wherein each of said SAMs is constructed as a multi-word length type and connected to a plurality of columns of said RAM, and each of said SAMs transmits/receives data to/from said memory cells belonging to said columns connected to said each of said SAMs, and each of said SAMs inputs/outputs data from/to the SAM port, whereby the data in said RAM are input/output as multi-bit data via said plurality of SAM ports of said plurality of SAMs, and wherein each of said SAMs is divided into first and second groups, the first group being accessed during a first half of a serial access time and said SAMs and the second group being accessed during a second half of said serial access time, and while one of said first and second groups serially outputs/inputs data, the other of said first and second groups transmits/receives data to/from said RAM.

Claim 12

A video memory device comprising a RAM and a plurality of SAMs, wherein said RAM is constructed of a plurality of memory cells disposed in a matrix having a plurality of rows and columns, one of said memory cells being selected through designation by row and column addresses, and one bit data being transmitted between said selected memory cell and a RAM port, said one bit data being input/output to/from the RAM port; and wherein each of said SAMs is constructed as a multi-word length type and connected to a plurality of columns of said RAM, and each of said SAMs transmits/receives data to/from said memory cells belonging to said columns connected to said each of said SAMs, and each of said SAMs inputs/outputs data from/to the SAM port, whereby the data in said RAM are input/output as multi-bit data via said plurality of SAM ports of said plurality of SAMs, and wherein each of said SAMs is divided into first and second groups, the first group being accessed during a first half of a serial access time and said SAMs and the second group being accessed during a second half of said serial access time, and while one of said first and second groups serially outputs/inputs data, the other of said first and second groups transmits/receives data to/from said RAM.

Claim 13

A video memory device according to claim 10, wherein each of said plurality of SAMs is made capable of being set at one of serial input and output modes, independently of each other.

Claim 14

A video memory device according to claim 11, wherein said first and second groups are alternately connected to said SAM ports by split selectors for the serial data input/output.

Claim 15

A video memory device according to claim 10, wherein said first and second groups are alternately connected via split selectors to said SAM ports for the serial data input/output.