Patent US5629877A successfully refreshed from Google Patents.
US5629877A
Expired / Lapsed
US
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Process and device composite simulation system and simulation method
Assignee: NEC Corp
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Filing: 1994-06-23
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Granted: 1997-05-13
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Expires: 2014-06-23
Abstract
Abstract A unified process and device simulation system unitarily performs simulation for a process design and a device design of a semiconductor device. The system includes a process simulator which performs a process simulation for one of a pair of regions of the semiconductor device. The regions are symmetric in configuration and structure about a center line which extends perpendicular to a direction about which the simulation is carried out. The process simulator generates a first simulation data. The system also includes a mirror reversal processing portion for performing a mirror reversing process for establishing a mirror data of the first simulation data symmetric about the center line on the basis of structure data of the semiconductor and connecting the mirror data to the first simulation data at the center line in order to generate a second data equivalent to a process simulation data obtained through the process simulation for an entire region of the semiconductor device. A device simulator then performs a device simulation with respect to the second data on the basis of a predetermined analysis condition.
Inventors
- 👤 Yukio Tamegaya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:48
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/44; G06F9/455; G06F30/00; G06F30/20; G06F30/23
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
174 words
A unified process and device simulation system unitarily performing simulation for a process design and a device design of a semiconductor device, comprising: a process simulator performing a process simulation for one of a pair of regions of the semiconductor device, said regions being symmetric in configuration and structure about a center line which is perpendicular to a direction about which the simulation is carried out, and generating a first simulation data; mirror reversal processing means for performing a mirror reversing process for establishing a mirror data of said first simulation data symmetric about said center line; extension data adding means for generating an extension data by extending the first simulation data and for adding said extension data between said first simulation data and said mirror data to generate a second data equivalent to a process simulation data obtained through the process simulation for an entire region of the semiconductor device; and a device simulator for performing a device simulation with respect to said second data on the basis of a predetermined analysis condition.
Claim 2
Dependent Claim
174 words
A unified process and device simulation system unitarily performing simulation for a process design and a device design of a semiconductor device, comprising: a process simulator performing a process simulation for one of a pair of regions of the semiconductor device, said regions being symmetric in configuration and structure about a center line which is perpendicular to a direction about which the simulation is carried out, and generating a first simulation data; mirror reversal processing means for performing a mirror reversing process for establishing a mirror data of said first simulation data symmetric about said center line; extension data adding means for generating an extension data by extending the first simulation data and for adding said extension data between said first simulation data and said mirror data to generate a second data equivalent to a process simulation data obtained through the process simulation for an entire region of the semiconductor device; and a device simulator for performing a device simulation with respect to said second data on the basis of a predetermined analysis condition.
Claim 3
Dependent Claim
69 words
A unified process and device simulation system as set forth in claim 1, wherein said mirror reversal processing means performs reversing process by copying said first simulation data to a memory region for data processing and reversing the order of the copied first simulation data for establishing said mirror data and generates said second data by coupling said mirror data to said first simulation data at said center line.
Claim 4
Dependent Claim
42 words
A unified process and device simulation system as set forth in claim 1, wherein said extension data adding means generates said extension data by extending the first simulation data corresponding to the center line of said semiconductor device to a predetermined length.
Claim 5
Dependent Claim
191 words
A unified process and device simulation system unitarily performing simulation for a process design and a device design of a semiconductor device, comprising: process simulator performing a process simulation for one of a pair of regions of the semiconductor device, said regions being symmetric in configuration and structure about a center line which is perpendicular to a direction about which the simulation is carried out, and generating a first simulation data; extension data adding means for generating an extension data by extending the first simulation data to a predetermined length and for adding said extension data to said first simulation data; mirror reversal processing means for performing a mirror reversing process for establishing a mirror data of said first simulation data and said extension data symmetric about the center line and connecting said mirror data to said first simulation data and said extension data to generate a second data equivalent to a process simulation data obtained through the process simulation for an entire region of the semiconductor device; and a device simulator for performing a device simulation with respect to said second data on the basis of a predetermined analysis condition.
Claim 6
Dependent Claim
191 words
A unified process and device simulation system unitarily performing simulation for a process design and a device design of a semiconductor device, comprising: process simulator performing a process simulation for one of a pair of regions of the semiconductor device, said regions being symmetric in configuration and structure about a center line which is perpendicular to a direction about which the simulation is carried out, and generating a first simulation data; extension data adding means for generating an extension data by extending the first simulation data to a predetermined length and for adding said extension data to said first simulation data; mirror reversal processing means for performing a mirror reversing process for establishing a mirror data of said first simulation data and said extension data symmetric about the center line and connecting said mirror data to said first simulation data and said extension data to generate a second data equivalent to a process simulation data obtained through the process simulation for an entire region of the semiconductor device; and a device simulator for performing a device simulation with respect to said second data on the basis of a predetermined analysis condition.
Claim 7
Dependent Claim
182 words
A unified process and device simulation system unitarily performing simulation for a process design and a device design of a semiconductor device, comprising: a process simulator performing a process simulation for one of a pair of regions of the semiconductor device, said regions being symmetric in configuration and structure about a center line which is perpendicular to a direction about which the simulation is carried out, and generating a first simulation data; mirror reversal processing means for performing a mirror reversing process for establishing a mirror data of said first simulation data symmetric about said center line; data cutting off means for cutting off a predetermined length of said first simulation data from the center line, and for connecting said first simulation data from which said predetermined length is cut off and said mirror data to generate a second data equivalent to a process simulation data obtained through the process simulation for an entire region of the semiconductor device; and a device simulator for performing a device simulation with respect to said second data on the basis of a predetermined analysis condition.
Claim 8
Dependent Claim
182 words
A unified process and device simulation system unitarily performing simulation for a process design and a device design of a semiconductor device, comprising: a process simulator performing a process simulation for one of a pair of regions of the semiconductor device, said regions being symmetric in configuration and structure about a center line which is perpendicular to a direction about which the simulation is carried out, and generating a first simulation data; mirror reversal processing means for performing a mirror reversing process for establishing a mirror data of said first simulation data symmetric about said center line; data cutting off means for cutting off a predetermined length of said first simulation data from the center line, and for connecting said first simulation data from which said predetermined length is cut off and said mirror data to generate a second data equivalent to a process simulation data obtained through the process simulation for an entire region of the semiconductor device; and a device simulator for performing a device simulation with respect to said second data on the basis of a predetermined analysis condition.
Claim 9
Dependent Claim
191 words
A unified process and device simulation system unitarily performing simulation for a process design and a device design of a semiconductor device, comprising: a process simulator performing a process simulation for one of a pair of regions of the semiconductor device, said regions being symmetric in configuration and structure about a center line which is perpendicular to a direction about which the simulation is carried out, and generating a first simulation data; data cutting off means for cutting off a predetermined length of said first simulation data from the center line; mirror reversal processing means for performing a mirror reversing process for establishing a mirror data with respect to said first simulation data from which said predetermined length is cut off symmetric about said center line and connecting said mirror data to said first simulation data from which said predetermined length is cut off to generate a second data equivalent to a process simulation data obtained through the process simulation for an entire region of the semiconductor device; and a device simulator for performing a device simulation with respect to said second data on the basis of a predetermined analysis condition.
Claim 10
Dependent Claim
191 words
A unified process and device simulation system unitarily performing simulation for a process design and a device design of a semiconductor device, comprising: a process simulator performing a process simulation for one of a pair of regions of the semiconductor device, said regions being symmetric in configuration and structure about a center line which is perpendicular to a direction about which the simulation is carried out, and generating a first simulation data; data cutting off means for cutting off a predetermined length of said first simulation data from the center line; mirror reversal processing means for performing a mirror reversing process for establishing a mirror data with respect to said first simulation data from which said predetermined length is cut off symmetric about said center line and connecting said mirror data to said first simulation data from which said predetermined length is cut off to generate a second data equivalent to a process simulation data obtained through the process simulation for an entire region of the semiconductor device; and a device simulator for performing a device simulation with respect to said second data on the basis of a predetermined analysis condition.
Claim 11
Independent Claim
158 words
A method for performing process and device composite simulation for unitarily performing simulation for a process design and a device design of a semiconductor device by an electronic computer, comprising the steps of: performing a process simulation for one of a pair of regions of the semiconductor device, said regions being symmetric in configuration and structure about a center line which extends perpendicular to a direction about which the simulation is carried out, and generating a first simulation data; performing a mirror reversing process for establishing a mirror data of said first simulation data symmetric about said center line and connecting said mirror data to said first simulation data at the center line in order to generate a second data; extending the first simulation data at said center line in the direction about which the simulation is carried out; and performing a device simulation with respect to said second data on the basis of a predetermined analysis condition.
Claim 12
Independent Claim
158 words
A method for performing process and device composite simulation for unitarily performing simulation for a process design and a device design of a semiconductor device by an electronic computer, comprising the steps of: performing a process simulation for one of a pair of regions of the semiconductor device, said regions being symmetric in configuration and structure about a center line which extends perpendicular to a direction about which the simulation is carried out, and generating a first simulation data; performing a mirror reversing process for establishing a mirror data of said first simulation data symmetric about said center line and connecting said mirror data to said first simulation data at the center line in order to generate a second data; extending the first simulation data at said center line in the direction about which the simulation is carried out; and performing a device simulation with respect to said second data on the basis of a predetermined analysis condition.
Claim 13
Dependent Claim
64 words
A simulation method as set forth in claim 7, wherein said mirror reversal process is performed by copying said first simulation data to a memory region for data processing and reversing the order of the copied first simulation data for establishing said mirror data and said second data is generated by coupling said mirror data to said first simulation data at said center line.
Claim 14
Dependent Claim
26 words
A simulation method as set forth in claim 7, wherein said extending step generates extension data by extending the first simulation data to a predetermined length.
Claim 15
Dependent Claim
25 words
A simulation method as set forth in claim 7, wherein said extending step is executed prior to the step of performing said mirror reversing process.
Claim 16
Dependent Claim
51 words
A simulation method as set forth in claim 7, further comprising the step of cutting off a predetermined length of said first simulation data from the center line, and connecting said first simulation data from which said predetermined length is cut off and said mirror data to generate said second data.
Claim 17
Dependent Claim
38 words
A simulation method as set forth in claim 7, further comprising the step of cutting off a predetermined length of said first simulation data from the center line prior to said step of performing said mirror reversing process.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-12 | 2000-11-11 | 2001-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-12 | 2004-11-11 | 2005-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-12 | 2008-11-11 | 2009-05-13 | $7700.00 | Window Closed / Lapsed |