System and method for assigning tags to control instruction processing in a superscalar processor

Claim 2

A superscalar processor, comprising: control logic that identifies an increment of advancement in the variable advance instruction window, requests an instruction source to send, to each of a plurality of register files, a portion of instruction information for a set of instructions equal in number to said increment of advancement, and assigns a tag to each new instruction that enters the variable advance instruction window, wherein said tag comprises a unique address in each of said plurality of register files where said portions of instruction information are to be stored; and a recycling queue comprising a plurality of slots equal in number to the predetermined size of the instruction window, each of said plurality of slots containing one of said tags, wherein an order defined by a position of said assigned tags in said recycling queue corresponds to the order of instructions in the variable advance instruction window.

Claim 3

The processor of claim 1, wherein said tags in each of said plurality of slots of said recycling queue are used to output said portions of instruction information from each of said plurality of register files.

Claim 4

The processor of claim 2, wherein said tags in each of said plurality of slots of said recycling queue are applied to read address ports of said plurality of register files to output said portions of instruction information, in program order, at corresponding read data ports of said plurality of register files.

Claim 5

The processor of claim 1, wherein the processor further contains a validity bit associated with each of said plurality of slots, wherein a validity bit of a particular slot identifies whether the corresponding portions of instruction information stored in said plurality of register files at the address identified by said tag in said particular slot are valid.

Claim 6

The processor of claim 4, wherein said recycling queue further contains a validity bit associated with each of said plurality of slots, wherein said validity bit associated with a particular slot identifies whether the corresponding portions of instruction information stored in said plurality of register files at the address identified by said tag in said particular slot is valid.

Claim 7

The processor of claim 1, wherein said control logic advances said tags in said recycling queue a number of slots equal to the number of instructions leaving the variable advance instruction window.

Claim 8

The processor of claim 1, wherein said recycling queue further comprises a plurality of multiplexers that select which tag goes into a particular slot when said recycling queue advances said increment of advancement.

Claim 9

The processor of claim 1, wherein decoded instruction information is stored in one of said plurality of register files.

Claim 10

The processor of claim 1, wherein a memory address of an instruction is stored in one of said plurality of register files.

Claim 11

The processor of claim 1, wherein information specifying functional unit requirements is stored in one of said plurality of register files.

Claim 12

The processor of claim 1, wherein information specifying a type of operation to be performed is stored in one of said plurality of register files.

Claim 13

The processor of claim 1, wherein a storage location of where instruction results are to be stored is stored in one of said plurality of register files.

Claim 14

The processor of claim 1, wherein a target address of an instruction is stored in one of said plurality of register files.

Claim 15

The processor of claim 1, wherein information specifying immediate data to be used in an operation specified by an instruction is stored in one of said plurality of register files.

Claim 16

A superscalar processor, comprising: control logic that identifies an increment of advancement in the variable advance instruction window, requests an instruction source to send, to each of a plurality of register files, a portion of instruction information for a set of instructions equal in number to said increment of advancement, and assigns a tag to each new instruction that enters the variable advance instruction window, wherein said tag comprises a unique address in each of said plurality of register files where said portions of instruction information are to be stored; and a recycling queue comprising a plurality of slots, each of said plurality of slots containing one of said tags, wherein an order defined by a position of said assigned tags in said recycling queue corresponds to the order of instructions in the variable advance instruction window, wherein said tags in said plurality of slots of said recycling queue are applied to read address ports of each of said plurality of register files to output said portions of instruction information, in program order, at corresponding read data ports of said plurality of register files.

Claim 17

A superscalar processor, comprising: control logic that identifies an increment of advancement in the variable advance instruction window, requests an instruction source to send, to each of a plurality of register files, a portion of instruction information for a set of instructions equal in number to said increment of advancement, and assigns a tag to each new instruction that enters the variable advance instruction window, wherein said tag comprises a unique address in each of said plurality of register files where said portions of instruction information are to be stored; and a recycling queue comprising a plurality of slots, each of said plurality of slots containing one of said tags, wherein an order defined by a position of said assigned tags in said recycling queue corresponds to the order of instructions in the variable advance instruction window, wherein said tags in said plurality of slots of said recycling queue are applied to read address ports of each of said plurality of register files to output said portions of instruction information, in program order, at corresponding read data ports of said plurality of register files.

Claim 18

The processor of claim 15, wherein decoded instruction information is stored in one of said plurality of register files.

Claim 19

The processor of claim 15, wherein a memory address of an instruction is stored in one of said plurality of register files.

Claim 20

The processor of claim 15, wherein information specifying functional unit requirements is stored in one of said plurality of register files.

Claim 21

The processor of claim 15, wherein information specifying a type of operation to be performed is stored in one of said plurality of register files.

Claim 22

The processor of claim 15, wherein a storage location of where instruction results are to be stored is stored in one of said plurality of register files.

Claim 23

The processor of claim 15, wherein a target address of an instruction is stored in one of said plurality of register files.

Claim 24

The processor of claim 15, wherein information specifying immediate data to be used in an operation specified by an instruction is stored in one of said plurality of register files.

Claim 25

The processor of claim 15, wherein said recycling queue comprises a plurality of slots equal in number to the predetermined size of the instruction window.

Claim 26

The processor of claim 15, wherein the processor further contains a validity bit associated with each of said plurality of slots, wherein a validity bit of a particular slot identifies whether the corresponding portions of instruction information stored in said plurality of register files at the address identified by said tag in said particular slot are valid.

Claim 27

The processor of claim 24, wherein said recycling queue further contains a validity bit associated with each of said plurality of slots, wherein said validity bit associated with a particular slot identifies whether the corresponding portions of instruction information stored in said plurality of register files at the address identified by said tag in said particular slot are valid.

Claim 28

The processor of claim 15, wherein said control means advances said tags in said recycling queue a number of slots equal to the number of instructions leaving the variable advance instruction window.

Claim 29

The processor of claim 15, wherein said recycling queue further comprises a plurality of multiplexers that select which tag goes into a particular slot when said recycling queue advances said increment of advancement.

Claim 30

A superscalar processor, comprising: a plurality of functional units; and a superscalar unit for receiving instructions from an instruction source and issuing instructions to said plurality of functional units, said superscalar unit comprising a monitoring system for tracking instructions in a variable advance instruction window having a predetermined size, said monitoring system comprising: a plurality of register files for storing portions of instruction information for instructions in said variable advance instruction window; control logic that identifies an increment of advancement in said variable advance instruction window, requests an instruction source to send, to each of said plurality of register files, a portion of instruction information for a set of instructions equal in number to said increment of advancement, and assigns a tag to each new instruction that enters said variable advance instruction window, wherein said tag comprises a unique address in each of said plurality of register files where said portions of instruction information are to be stored; and a recycling queue comprising a number of slots equal to said predetermined size of said variable advance instruction window, each of said slots containing one of said tags, wherein an order defined by a position of said assigned tags in said recycling queue corresponds to the order of instructions in said variable advance instruction window; wherein said tags in each of said plurality of slots of said recycling queue are applied to read address ports of each of said plurality of register files to output said portions of instruction information, in program order, at corresponding read data ports of said plurality of register files.

Claim 31

A superscalar processor, comprising: a plurality of functional units; and a superscalar unit for receiving instructions from an instruction source and issuing instructions to said plurality of functional units, said superscalar unit comprising a monitoring system for tracking instructions in a variable advance instruction window having a predetermined size, said monitoring system comprising: a plurality of register files for storing portions of instruction information for instructions in said variable advance instruction window; control logic that identifies an increment of advancement in said variable advance instruction window, requests an instruction source to send, to each of said plurality of register files, a portion of instruction information for a set of instructions equal in number to said increment of advancement, and assigns a tag to each new instruction that enters said variable advance instruction window, wherein said tag comprises a unique address in each of said plurality of register files where said portions of instruction information are to be stored; and a recycling queue comprising a number of slots equal to said predetermined size of said variable advance instruction window, each of said slots containing one of said tags, wherein an order defined by a position of said assigned tags in said recycling queue corresponds to the order of instructions in said variable advance instruction window; wherein said tags in each of said plurality of slots of said recycling queue are applied to read address ports of each of said plurality of register files to output said portions of instruction information, in program order, at corresponding read data ports of said plurality of register files.

Claim 34

The method of claim 29, further comprising the step of advancing said queue a number of slots equal to the number of new instructions determined to be added to the instruction window.

Claim 35

The method of claim 29, wherein said step (d) comprises the step of storing decoded instruction information.

Claim 36

The method of claim 29, wherein said step (d) comprises the step of storing a memory address of the instruction.

Claim 37

The method of claim 29, wherein said step (d) comprises the step of storing information specifying functional unit requirements.

Claim 38

The method of claim 29, wherein said step (d) comprises the step of storing information specifying a type of operation to be performed.

Claim 39

The method of claim 29, wherein said step (d) comprises the step of storing information specifying a storage location where instruction results are to be stored.

Claim 40

The method of claim 29, wherein said step (d) comprises the step of storing information specifying a storage location where instruction operands are stored.

Claim 41

The method of claim 29, wherein said step (d) comprises the step of storing information specifying a target address of an instruction.

Claim 42

The method of claim 29, wherein said step (d) comprises the step of storing information specifying immediate data to be used in an operation specified by the instruction.

Claim 43

The method of claim 31, further comprising the step of storing a valid bit for each tag in said queue, wherein when valid bit is set if the instruction corresponding to the tag associated with the valid bit is valid.

Claim 44

The method of claim 29, wherein said step (d) comprises the step of storing instructions.

Claim 47

The method of claim 41, further comprising the step of: (d) using said tags stored in said slots of said queue to output said portions of instruction information in said plurality of register files in program order.

Claim 48

The method of claim 42, wherein step (d) comprises the step of passing said tags stored in said slots of said recycling queue to a plurality of read address ports of said plurality of register files to cause said plurality of register files to output said portions of instruction information, in program order, at a plurality of read data ports of said plurality of register files.

Claim 49

The method of claim 41, wherein said step (b) comprises the step of storing decoded instruction information.

Claim 50

The method of claim 41, wherein said step (b) comprises the step of storing a memory address of the instruction.

Claim 51

The method of claim 41, wherein said step (b) comprises the step of storing information specifying functional unit requirements.

Claim 52

The method of claim 41, wherein said step (b) comprises the step of storing information specifying a type of operation to be performed.

Claim 53

The method of claim 41, wherein said step (b) comprises the step of storing information specifying a storage location where instruction results are to be stored.

Claim 54

The method of claim 41, wherein said step (b) comprises the step of storing information specifying a storage location where instruction operands are stored.

Claim 55

The method of claim 41, wherein said step (b) comprises the step of storing information specifying a target address of an instruction.

Claim 56

The method of claim 41, wherein said step (b) comprises the step of storing information specifying immediate data to be used in an operation specified by the instruction.

Claim 59

The method of claim 52, wherein said step (c) comprises the step of storing each tag in a slot of a recycling queue, said recycling queue comprising a plurality of slots equal in number to the predetermined size of the instruction window.

Claim 60

The method of claim 52, wherein said step (b) comprises the step of storing decoded instruction information.

Claim 61

The method of claim 52, wherein said step (b) comprises the step of storing a memory address of the instruction.

Claim 62

The method of claim 52, wherein said step (b) comprises the step of storing information specifying functional unit requirements.

Claim 63

The method of claim 52, wherein said step (b) comprises the step of storing information specifying a type of operation to be performed.

Claim 64

The method of claim 52, wherein said step (b) comprises the step of storing information specifying a storage location where instruction results are to be stored.

Claim 65

The method of claim 52, wherein said step (b) comprises the step of storing information specifying a storage location where instruction operands are stored.

Claim 66

The method of claim 52, wherein said step (b) comprises the step of storing information specifying a target address of an instruction.

Claim 67

The method of claim 52, wherein said step (b) comprises the step of storing information specifying immediate data to be used in an operation specified by the instruction.

Claim 68

The method of claim 52, wherein said step (d) comprises the step of applying said tags to read address ports of said plurality of register files to output said portions of instruction information, in program order, at corresponding read data ports of said plurality of register files.