Predictive historical cache memory

Claim 2

In a system having a processor and a memory system which includes a part predictive part historical cache memory, a method of halting the prefetching of instructions to the cache memory when the ratio of the predictive part to the historical part of the cache memory becomes greater than a predetermined ratio, the method comprising the steps of: maintaining a first register which contains a word having a value which defines a first pointer to a location in the cache memory which held a last instruction provided to the processor from the cache memory; and maintaining a second register having a predetermined number of contiguous zero-bits and having a predetermined number of one-bits forming a word, a ratio of the number of zero-bits to the number of one-bits corresponding to a desired ratio of the historical to predictive parts of the cache memory, the bit position having a value of zero that is immediately to the left of and adjacent to the contiguous bits having a value of one, corresponding to a location in the cache memory incremented by one location from where a last prefetched instruction was stored in the cache memory; ANDing each bit of the first register with each respective bit of the second register to yield an ANDed word having a number of bits corresponding to the number of bit positions of the first and second registers; ORing each of the bits of the ANDed word to yield a single bit value corresponding to a prefetch control signal; and halting prefetching of instructions when the prefetch control signal has a zero value.

Claim 3

In a switching system having a processor, a main memory, and a cache memory for temporarily storing instructions, a circuit for maintaining a cache memory as a part historical, part predictive circular buffer, the circuit comprising: a logic circuit including a plurality of pointer registers including a first pointer register for containing a word having a value which is expressed in a predetermined number of bits and defines a first pointer indicating a first location in the cache memory which held a last instruction provided to the processor from the cache memory, and a second pointer register for containing a word having a value which is expressed in a predetermined number of bits and defines a second pointer indicating a second location in the cache memory where a last prefetched instruction was stored, the logic circuit further monitoring if a positional difference between the first and second pointers exceeds a predetermined amount; and a prefetching circuit responsive to control signals from the processor and the logic circuit for fetching instructions upon requests from the processor and for prefetching instructions from the main memory to the cache memory upon requests from the logic circuit wherein the prefetching circuit is prevented from performing the prefetching by the logic circuit when the positional difference between the first and second pointers exceeds the predetermined amount; wherein the value of the word in the second pointer register is expressed in a preset number of binary bits which have a predetermined number of contiguous zero bits and a predetermined number of one-bits, the number of zero bit values to the number of one-bit values being adjustable and corresponding to a desired relationship between the historical part and the predictive part of the cache memory.

Claim 4

In a switching system having a processor, a main memory, and a cache memory for temporarily storing instructions, a circuit for maintaining a cache memory as a part historical, part predictive circular buffer, the circuit comprising: a logic circuit including a plurality of pointer registers including a first pointer register for containing a word having a value which is expressed in a predetermined number of bits and defines a first pointer indicating a first location in the cache memory which held a last instruction provided to the processor from the cache memory, and a second pointer register for containing a word having a value which is expressed in a predetermined number of bits and defines a second pointer indicating a second location in the cache memory where a last prefetched instruction was stored, the logic circuit further monitoring if a positional difference between the first and second pointers exceeds a predetermined amount; and a prefetching circuit responsive to control signals from the processor and the logic circuit for fetching instructions upon requests from the processor and for prefetching instructions from the main memory to the cache memory upon requests from the logic circuit wherein the prefetching circuit is prevented from performing the prefetching by the logic circuit when the positional difference between the first and second pointers exceeds the predetermined amount; wherein the value of the word in the second pointer register is expressed in a preset number of binary bits which have a predetermined number of contiguous zero bits and a predetermined number of one-bits, the number of zero bit values to the number of one-bit values being adjustable and corresponding to a desired relationship between the historical part and the predictive part of the cache memory.